User name R. Michaels
Log entry time 15:22:50 on March30,2007
Entry number 197673
This entry is a followup to: 197590
keyword=trigger prep, part IIMore work on the trigger --
T2 is now the "or" of S1,S2 as it was last December.
S0 detector is removed from detector stack.
R-arm retiming (RT) is satisfactory, but L-arm RT is "marginal"
(see below). Nothing we can do about it since the analog delays
are fixed and the experiment wants beta=0.21 !!
What I mean by "marginal" RT on Left HRS:
For T5 the difference from L1A to RT is presently 32 nsec (tight!).
This was after adding 24 nsec to RT from the previous experiment.
Since T5 timing is normally determined by T3, this will
remain fixed. However, for randoms in which T3 is too early,
an ugly situation arises: the L-arm gates are "forced retimed"
and end up having R-arm timing. This will occur over the
last 14 nsec of the random coinc. range.
This is because of design of RT circuit: If RT is too early
(e.g. a pileup) a gate is generated with timing of L1A, and so if
T3 is early (random coinc) the L1A has T1 timing. (For completeness,
if RT is absent one also gets a gate, but 200 nsec late, with
L1A timing. It's a basic idea that we must always get a gate.)
So, what prevents me from simply increasing the time diff
of L1A to RT (from 32 to say, 50) ? The scint. TDC dynamic
range is tight. If the TDCs are below 50 nsec (chan 1000) they
can become nonlinear. Fig 1 shows the worse case -- for s1.
I didn't show s2 because its better. This was run 2037.
I decide we can live with this setup.
T6 and T7 do not exist yet. Alex is working on it.
When they do, if they are timed in with T5 at the
Trig. Super, we'll be fine.
T6 = T3.and.R-arm-RT
T7 = T4.and.T1
FIGURE 1
