Status Report

Date: 20 April 2012

• 1. FADC analyzer
• 2. DAQ upgrading
• 3. ToDo List

FADC analyzer.

1. Helicity trigger.

•   We don't see any problems to analyzing FADC Scalers data (from helicity trigger).
  The asymmery result from FADC scalers and old DAQ is in good agreement.

2. Data trigger issues.

•   Helicity counter and helicity state unsynchronized.
  There is 10 bits counter of helicity windows in data triggers stream (0x3ff0000 & B.fadc.sidechan[0]).
  Helicity state bit for data trigger stored in word (0x8 & B.fadc.sidechan[0]).
  Some times during the run the states of helicity window and helicity counter reported by FADC are losing synchronization.
  Another words, helicity counter has been incremented by one for next helicity window (with opposite sign, for example),
  but helicity state bit is still unchanged for few next data triggers Run #2387 Pic.1.
  It gives wrong helicity state for that windows. Number of data triggers with wrong helicity state for
  one window is changed during run in range from 0-50% of all triggers per window.
  It means that data trigger helicity state should be checked with helicity state that recorded by module QDC V792.
  

•   "Empty" Data Triggers.
  There are many data triggers without signals that have produced these triggers in the root file (Run# 2683 Pic.2. Pic.3. )
  We are ivestigating this problem, but still do not have good understanding.
  There are two possibility.
  First one is FADC saved wrong trigger type for data trigger.
  Second one is trigger type is right, but signals from some ADC channels did not stored into data buffer.
  

Moller Detector Electronics Upgrading.

The main goals of the electronic upgrading for the Moller Polarimeter are next:

• increase bandwidth (up to 200MHz) of the detector system
• reduce readout time from ADC and TDC modules
• replace old PLU module 2365, that does not produced any more

The list of modules to be replaced:

• Increase bandwidth:
  • PLU module LeCroy-2365, bandwidth <75 MHz, CAMAC
        <-- replaced by PLU module based on CAEN V1495 board (bandwidth 200MHz, VME)
    
  • Discriminator   Ortec-TD8000, input rate <150 MHz, CAMAC
        <-- replaced by P/S 706 (300 MHz, NIM), modified for remote threshold setup with DAC type of VMIC4140
    
• Reduce readout time:
  • ADC LeCroy 2249A, 12 channels, CAMAC
        <-- replaced by QDC CAEN V792 (32 channels, VME) *
    
  • TDC LeCroy 2229, CAMAC
        <-- replaced by TDC V1190B (64 channels, 0.1ns, VME)

Programmable Logical Unit based on V1495 module.

CAEN V1495 Module:

• Input bandwidth ~200 MHz
• 2 input ports x32 bits
• 1 output port x32 bits
• 2 input/output front LEMO connectors
• FPGA "User" can be free reprogrammed by the user with own custom logic function

Firmware for PLU module is developed ( PLU Diagram ).
Module has been programmed with next units:

• Programmable Logical Unit (PLU): 16 inputs, 16 outputs
• Scalers unit: 16 channels, 32 bit, gate input, connected to PLU outputs
• Free running 64 bit timer with base frequency 40 MHz
• Programmable Generator Unit: ~1 kHz - 10 MHz output rate, pulse width 10-50 ns (to be implemented)

We considering also to do implementation of some triggers unit (for ADC, TDC trigger and gate).
Extension I/O Piggyback board type of A395D (8 programmable I/O, NIM) is required (cost ~$400).

What we have.

1. Stand with VME and NIM crates for testing of electronic modules.
2. Firmware for PLU module is under developing and testing.
3. Software:

• Library to control DAC for remote threshold setup is ready.
• Library for configuring and controlling of PLU module is ready ( Logical Unit and Scalers).
• Readout list for TDC and PLU Scalers is ready.
• Coda is running for testing TDC and PLU modules.

ToDo List.

Code to analyzing Data Trigger of FADC DAQ

Firmware optimization and finalizing for PLU module

Testing of PLU+TDC+QDC with CODA

Analyzer modification for old DAQ.

Migration of both DAQ's to CODA 3 ( configuration files, mSQL DB, CRL code)