helicity timing board in hall A

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User name R. Michaels

Log entry time 13:13:09 on February14,2013

Entry number 385791

keyword=helicity timing board in hall A

A helicity timing board was setup in the Compton FADC development
crate. The library is in adaq1:~adev/vme/helboard
see drvHEL (lib) and setupHel (code to set up).

The defaults loaded upon boot-up of vxWorks are:

T_settle = 100 usec
T_stable = 1 msec (hence 1 kHz helicity flip)
Helicity pattern octet
reporting delay zero

Other values can be loaded at the vxWorks prompt, e.g.

-> setupHel(9,6,0,2)

The power-up state of the board is observed to be

T_settle = 100 usec
T_stable = 2 msec (hence 500 Hz)
Helicity pattern - nonsense since pattern synch is at 15 Hz

Since the power-up state is nonsense, it is necessary to program
a default setting, which we do.

I have not ported this code to Intel (Linux) yet.

Also note: the first fiber optic is an input for Line Sync.
At present, there is nothing plugged in, so the helicity board
is not synched to 60 Hz (this is also observable on a scope
by triggering on 60 Hz). This will cause some trouble for
high-precision asymmetry studies, if we don't synch.