Index of /parity/prex/adc18

	Name	Last modified	Size	Description
	Parent Directory		-
	ADC1.PDF	28-Nov-2007 08:28	84K
	ADC2.PDF	28-Nov-2007 08:28	84K
	ADC3.PDF	28-Nov-2007 08:29	84K
	ADC4.PDF	28-Nov-2007 08:29	85K
	DAC.PDF	28-Nov-2007 08:29	70K
	FPGA.PDF	28-Nov-2007 08:31	198K
	FPGA_PROG.PDF	28-Nov-2007 08:31	88K
	HALLA_ADC.ZIP	28-Nov-2007 09:26	1.6M
	INPUT1.PDF	28-Nov-2007 08:27	71K
	INPUT2.PDF	28-Nov-2007 08:27	70K
	INPUT3.PDF	28-Nov-2007 08:27	71K
	INPUT4.PDF	28-Nov-2007 08:28	71K
	IO.PDF	28-Nov-2007 08:30	113K
	PLD.PDF	28-Nov-2007 08:31	241K
	POWER1.PDF	28-Nov-2007 08:30	87K
	POWER2.PDF	28-Nov-2007 08:30	49K
	POWER3.PDF	28-Nov-2007 08:32	77K
	README	18-Jul-2008 16:45	606
	VME.PDF	28-Nov-2007 08:30	148K
	adc18.pdf	18-Jul-2008 16:52	448K
	adc18.ps	18-Jul-2008 16:51	4.5M
	adc18.tar	18-Jul-2008 16:52	10M
	prex_adc18_spec.ps	17-Jul-2008 12:31	134K

July 2008.  Report on ADC18 tests

  adc18.ps   postscript version
  adc18.pdf  PDF version
  adc18.tar  tarball, do this: "tar xvf adc18.tar"
                      and see README in ./adc18

December 2007
18-bit ADC design drawings from Fernando Barbosa

Analog frontend of 4 channels of ADC (they are identical)
  INPUT1.PDF
  INPUT2.PDF
  INPUT3.PDF
  INPUT4.PDF

4 channels of ADC (they are identical)
   ADC1.PDF
   ADC2.PDF
   ADC3.PDF
   ADC4.PDF

The DAC noise
   DAC.PDF

Other details of the design
  FPGA.PDF
  FPGA_PROG.PDF
  IO.PDF
  PLD.PDF
  POWER1.PDF
  POWER2.PDF
  POWER3.PDF
  VME.PDF