In attendance: Dave Abbott, Fernando Barbosa, Jian-Ping Chen, 
Peter Bosted, Eugene Chudakov, James Proffit, Ed Jastrzembski, 
Robert Michaels, Xiaochao Zheng.

- Fernando presented some studies on the FADC requirement and survey for 
  JLab future projects. His slides can be found at
    http://hallaweb.jlab.org/experiment/E05-007/daq/minutes/FADC_Electronics_Workshop.pdf
 - Bob questioned if we buy new VME crates, should we buy VME64x and 
   greater? The answer is yes.

- Xiaochao presented schematic diagrams for the test plan to be done 
  on the right HRS.  A write-up can be found at
    http://www.jlab.org/~xiaochao/pvdis/daq/daqtest1.ps
Some comments on the diagram:

 1) Should add (regular) ADCs to the preshower and shower sum to determine
    the discriminator threshold level; (Jian-Ping)
 2) The discriminator will have considerable time-walk. May want to try
    constant-fraction triggering; (Eugene)
 3) For the test, may want to send regular trigger to 2nd floor to identify
    "good" events (Jian-Ping etc); or sending the scintillator signals;  Is 
    this feasible?
 4) We should worry about doule-pulsing of the PMTs (Peter), which  
    definitely exists on some bad PMTs (Bob);
 5) Will add one more scaler with delay unit in one of the inputs to measure
    accidental coincidence (Xiaochao);
 6) For the experiment should consider summing up a subset of detector 
    blocks instead of summing them all (e.g. 80 blocks of the Shower); Should
    consider using similar algorithm as the GEN detector; (Jian-Ping)

- David brought in the FADC module that we can borrow for the test
  (Struck SIS3300, 100MHz sampling rate, VME64x, 8 channels, 12-bit). 
  Thanks!
  David commented that there are three ways to add triggering to FADC:
  1) external triggering provided by NIM electronics;
     (and we can try this one during the test)

  2) on-board triggering provided by the on-board data processing;
  3) on-board triggering provided by FPGAs;

- About the sampling frequency of FADCs:
  - 100MHz is good enough for the test, since the signal at the 2nd floor 
    will be wide (a few 10ns) after the long cabling from the hut;
  - The output signals of right HRS Shower PMTs are typically 20ns wide
    (Eugene), so 250MHz FADCs, not 65MHz ones (see chip survey in Fernando's
    talk), will be the one we will eventually use.

- We discussed on the timeline of the FADC project (see last slide of Fernando's
  presentation).  The users (Hall A) should provide main algorithm for event 
  identification (we will figure this out from the test) and specifications
  for the FADC (some of us need to do simulations for that, combined with the
  test result).

*** The Plan ***
  We will set up the test this month and hopefully start some simulations.