********************************************************* Changes made to the right arm DAQ, and to-do list ********************************************************* DAQ to do: 1) Is VETO truly deadtime-less now? 2) pulser test for right arm tagger system - done 7/22 with HRS DAQ only, got pileup results, Kai is analyzing them; 3) change GC width to 20ns; 4) check why gr5-8 for tagger are later than gr1-4 by 10ns. 5) EDTM for T1 and GC? A) John reminded me that the same "pileup" scheme should be done for EDT pulsers too. Is it possible to send this to TDCs? B) Can send multiple copies of T1 with different width (20, 50, 100, 150, 200ns etc) to scalers and compare counts. 6) If T1 is by itself 100ns wide, deadtime of the T1 circuit is already 100ns. THis means we should extend our VETO to >100ns wide. Same for GC. According to Bogdan the GC pulse duration is (guessed) 100-120ns but can be reduced to 50-60ns. Note: Ramesh said the T1 is made 100ns to avoid after-pulsing. John said the same thing. 7) replaced the NIM/ECL which seem to have unstable input for ch1-2. Now are VETO "double TDC pulse" still there? (need beam). 8) Possible tests to do during HAPPEX: a) Use S1 and S2 to test deadtime/VETO: i) Use matching paddles to form T1, fan it out as GC; (how does prescaling work? Can we choose 1 out of 2 T1 as GC?) ii) Use unmatching paddles to simulate leadglass pulses, fan it out as both PS and SH; iii) make sure the timing of TS, PS inputs to the ANDing module is 3-5ns behind the VETO (close to real situation). Analysis to do: 1) Longitudinal target results with dilutions corrected - done, see Xiaoyan's page 2) Transverse target results (group en, ew) with dilutions corrected. - done, see Xiaoyan's page 3) Deadtime rate scan with accidental coincidence corrected? <- after July 27 4) Accidental coincidence consideration in general, design possible measurements. 5) BCM calibration using previous data for non-linearity analysis. Runplan should contain: 1) Commissioning: optics, boiling test; 2) daily low currnt run for: Q2, PID, other stuff? 3) dedicated runs for accidental coincidence measurement? ************************************************************************************************************************* 7/27/2009 (Diancheng/Kai) 1) A copy of T1 (in addition to the two existing copies) is sent to downstairs using a new cable. This T1 goes to back rack. The three fan-outs go to: PS 740 gr3, TS 740 gr3, and the front rack. The cable to the front rack was connected to NIM/ECL #5, ch4, until 7/28 9am. Afterwards it was left on the side and not terminated. The cable originally in NIM/ECL #5/ch4 (T1+tagger from the VETO circuit) was disconnected between 7/27 evening and was restored around 7/28 9am. 2) The eVETO to gr1-4 electrons were disconnected and then restored around 7/28 9am. 3) The CH tagger cable going from the front to the back rack was disconnected and then restored around 7/28 9am. ************************************************************************************************************************* 7/27/2009 Use the T1 copy (see 7/21 item 5)), previously: T1 from upstairs (2x16ns) -> 8ns cable -> 706 (2nd channel on DHw30ns) -> 5ns cable -> 755 input ^ 2nd output was terminated now: ^ 2nd output is going to 3 spare channels in 758 (tagger fanout module), chained to produce 3 copies of T1. These are sent to NIM/ECL #5 using 16ns yellow cables: width NIM/ECL ch 758 ch 6 125ns #5/ch6 758 ch 7 150ns #5/ch7 758 ch 8 25ns #5/ch8 (had problem adjusting width of this one) NIM/ECL #5/ch5 is a direct copy of T1 from upstairs, which has 100ns output width. ************************************************************************************************************************* 7/22/2009 CH tagger has double pulsing. The two cables in the counting house middle room are mislabeled: "rhrs tagger" is actually going to left hrs, and was NOT terminated! "lhrs tagger" is actually going to the right hrs, and because of the un-terminated cable, has double-pulsing 1us apart. The "rhrs tagger"-labeled cable was disconnected from the middle room and additional labels were made to indicate the actual going-where of the two cables. ************************************************************************************************************************* 7/21/2009 1) Added 16ns delay cables to: gr1-4, PS Sum8 to TS 740; gr1-4, SH Sum8 to TS 740; these combined with the extra 7(8)ns delay on the PS branch should take care of the delays needed by gr1-4, as follows: Previously: a) gr1-4 TSDH were too early by ~8ns compared to PSDM, shown in http://hallaweb.jlab.org/experiment/E05-007/meetings/testrun_may09/time_diff/run_22517/nocut_ts-minus-ps.pdf b) gr1-4 electron triggers are early by ~5ns compared to gr5-8). Note: now there is a possibility that gr1-4 electrons are late than gr5-8 by 2-3ns or more. This has to be monitored at the beginning of the run. If they do, can remove some of the 16ns delays added here (replace by 8ns, for example). c) Pion triggers for gr1-4 are about 16ns earlier than gr5-8, and partly miss the piVeto. 2) Changed narrow discriminators to 30ns, for DL, DM and DH. This should further eliminate the loss in narrow paths due to missing coincidences, indicated by the difference between red and blue in http://hallaweb.jlab.org/experiment/E05-007/meetings/testrun_may09/time_diff/run_22517/nocut_ts-minus-ps.pdf 3) Checked timing of delayed tagger vs. signal for all 8 groups: delayed tagger --------+ +---------- input to tag/sig coin | | (60ns width) +------------+ signal input to tag/sig coin------------+ +--------------- (20-25ns width) | | +---+ ->| |<- t1 path t1 1n 14ns 1w 18ns 2n 14 2w 20 3n 14 3w 20 4n 14 4w 20 5n 20 5w 34 6n 30 6w 34 7n 25 7w 34 8n 22 8w 32 3) Checked PS, TS inputs to 758: coincide within 2ns for all 16 channels (en and ew); 4) Checked VETO vs. tagger PS, TS inputs: +--------------------+ VETO | | -----+ +-------------------------- PS or TS in -------------+ +--------------------------- | | +---+ |<-t2->| t2 = 10ns for gr1-4 en, 20ns for gr1-4 ew, 20ns for gr5-8 en, 30ns for gr5-8 ew 5) Changed T1 input to VETO: previously: T1 from upstairs (2x16ns) -> 14ns cable -> 5ns cable -> 755 input now: T1 from upstairs (2x16ns) -> 8ns cable -> 706 (2nd channel on DHw30ns) -> 5ns cable -> 755 input ^ extra delay measured to be 5ns. 6) Changed width in VETO circuit: 1st and 2nd output width set to 30ns (previously 50ns for GC and 20ns for T1). ************************************************************************************************************************* 7/20/2009 1) Added tagger to gr1-4 on the back rack using 2 LeCroy 428F. PS mixing with tagger: did not use extra cable, disconnected white thick delay cable from yellow ones (yellow ones go to DMs on the front rack), and added 428F in between. Extra delays caused by 428F is measured to be 7ns for ch1n; ************************************************************************************************************************* 7/17/2009 1) "Cleaned up" tagger setup on the front rack. Now the tagger setup is http://www.jlab.org/~xiaochao/pvdis/daq/diagrams/current/tagger_setup.png 2) Added tagger to group 1-4 on the front rack (coin circuits). Now the 2nd last NIM crate contains, from left to right: 757 for fanning out delayed tagger; 757 for inverting gr5-8, en and ew; 757 for inverting gr1-4, en and ew; 758 for ANDing tagger with gr1-4, en and ew; outputs are sent to NIM/ECL #5, ch9-16 758 for ANDing tagger with gr5-8, en and ew; output to NIM/ECL already existed (used since May 19) ************************************************************************************************************************* 7/15/2009 Reason for VETO deadtime: 1) timing for tagger and physics signals are different: Physics signals: PSDM and TSDH inputs to ANDing module are only slightly behind VETO because T1 and GC come in very late to the PVDIS rack. -------------------------------------+ +--------- | | T1 (supposed to be 100ns wide according to Ramesh) +-----------+ ------------------------------------+ +------------ | | GC (75ns wide measured on the scope) +--------+ ---------------------------------------+ +--------- | | eVETO (100ns wide) input to 758 +-----------+ -------+ +----------------------------------------- | | PS input from PMTs +--+ -------+ +----------------------------------------- | | SH input from PMTs (actually ~35ns later than PS) +--+ |<------multiple delays----->| ----------------------------------------+ +--------- | | PSDM input to 758, only slightly behind VETO +--+ ----------------------------------------+ +--------- | | TSDH input to 758 +--+ Tagger: Tagger is being fan-out to T1 and GC at the same time as to PS and TS. Also, There are long cables to send the splitted tagger from the front to the back rack where it is mixed with PS and TS. There is a roughly 50ns delay between VETO input and the PSDM, TSDH inputs to the ANDing module. -------+ +----------------------------------------- | | PS input from PMTs +--+ -------+ +----------------------------------------- | | SH input from PMTs (actually ~35ns later than PS) +--+ ---------+ +---------------------- | | eVETO from tagger +-------------------+ |<-->| long cable from front to back rack --------------+ +---------------------------------- | | Input to mix with PS +--+ --------------+ +---------------------------------- | | Input to mix with SH +--+ |<>| long cable from back to front rack -----------------+ +---------------------------------- | | PSDM input to 758 +--+ -----------------+ +---------------------------------- | | TSDH input to 758 +--+ |<----->| PSDM and TSDH inputs are about 50ns behind VETO to 758 2) 755 is NOT ALWAYS updating: (A) senario A (updating): when input 2 occurs after input 1 resets to zero, and before the output width (wo) is reached (triggred by input 1), the output will be extended. I.e., falling edge of output is t1, rising edge is t2+wo if (t2-t1)>wi1 and (t2-t1)wo), the output triggered by input 1 already returns to zero and there is no 2nd output triggred by input 2. I.e., falling edge of the only output is t1, rising edge is t1+wo if (t2-t1)wo. There is no 2nd output. input 1 -------+ +----------------- | | +-------------------+ t1 (width wi1) input 2 ------------------------+ +------------------------- | | +--+ t2 (width wi2) OR output -------+ +------------------------- | | NO second output! +------------+ t1 t1+wo wo = set output width of 755 3) Since the input T1 is 100ns wide and GC is 75ns, the non-updating feature of 755, COMBINED with the long delay between tagger PSDM, TSDH inputs and the VETO inputs to the 758, cause a deadtime in the VETO circuit. This deadtime is expected to be about 50ns: when tagger occurs within the 2nd 50ns of a previous T1 input, its PS/TS would miss the VETO triggered by the T1 and the tagger itself does not trigger the VETO circuit. Plots of tagger fractional loss vs. T1 and GC rate reveals results of 63ns and 69ns for the deadtime, respectively. 4) These were not reproduced in the offline pulser test because pulser inputs to T1 and GC were 20ns wide. Also, they follow exactly the same timing sequence as the tagger itself (same fan-out and mixing with PS/TS scheme). Although, it's the combination of both that caused VETO deadtime during 5-pass test runs. 5) Solution: a) Adjust timing such that tagger PS/TS inputs are not too much behind VETO input to the 758. Ideally, this should be of 10ns level; b) Change T1 and GC input pulse width to 30ns, and all width of 755 output to be 30ns except the last fan-out channels.