Signals generated for coincidence trigger : -T1 output from mixed logic was sent to discriminator group 2, the output signal was set to 150 ns -T3 output from mixed logic was sent to discriminator group 4, the output signal was set to 30 ns
the two signal were fed to the logic module to make coincidence. The T5 signal was sent to NIM/ECL module in top CAMAC crate on channel 10 ( channel 11 seems to be bad )
coincidence trigger was fed to TS.
Added additional delay for T1 going to TS now is going through additionnal delay RDelay channel 7 and 8 now set at 8 and 8.
T2 was already delayed : it is on RDelay1 channel 11 to 13
T3 was restored as previously and is on RDelay2 channel 1 and 2.
Left to be done for the trigger :
-split and delay T4 to go in TS
-check retiming and gate to be compatible with T5 timing ( retiming might
need to be delayed a bit to avoid forced retiming this will be done after
CSR )
-check/recable coincidence time ( this will be done tomorrow during
energy change )
A copy of this log entry has been emailed to: rom@jlab.org