We then ran the signal for PMT 5 from the patch panel, through the gate and back up to the ADC cable. Total additional delay on the signal was 8ns + 8ns (cables) + 10 ns (internal delay in the gate module) = 26 ns.
The linear gate was gated using the !NIM (inv-NIM) output of the GDG generator that makes the ADC gate for the v792. The timing of the signal at the linear gate is such that it clips the signal ~10ns before the ADC gate closes (effectively making the ADC gate 10ns shorter for PMT 5 only).
The CAMAC crate was powered off in order to install the linear gate
module. We powered it back on and ran the CAMAC crate init script and
edtm script. The discrim. levels and EDTM T5 coin. timing was explicitly
confirmed using a DVM and the 'scope.
A copy of this log entry has been emailed to: zhangyi