Log entry time 16:58:28 on August31,2009

Entry number 287249

Sometimes the DAC noise "glitches" leading to a glitch in
the signal (see fig 1).  This was happening in the test crate too,
and it seems worse with oversampling; though maybe it's not worse
but you are more likely to see it because of the higher rate.
This happens on all channels and on ALL boards in the crate 
simultaneously, so it might be timing board related.  It would be 
easy to cut out of the data -- look at base or peak, see a 
discontinuity -- but I need to see if I can eliminate this in 
the Test Crate.

On a brighter note, some low-level checks pass:  the CSR is always
normal (no event-buffer full conditions, etc), the event counters 
are always synched, the word count is stable, the order of the 
data is never scrambed.  With this CRL version the first 1 to 5 events
get the "bad1" flag, but after that its clean.  If I get a chance
to roll out the new CRL only the 1st event should be bad.