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User name jroche
Log entry time 15:24:16 on September15,2010
Entry number 332277
This entry is a followup to: 332265
keyword=LHRS testing the detector map (ct'd)This is a follow up to my entry from this morning. I have been educated on a few things and "figured out" the S2.
-S2 Right: I had seen two issues.
--On these tubes I saw no adc signal and very large pedestal: indeed inverting the polarity of the signal going into the ADC fixed that (see plot 1: fixed, plot 2: bad).
--HV channel drawing no current. The signal from s2ML07 is plugged on the next HV board at channel 14. To avoid confusion I set the desired voltage on the S2ML board channel 6 to 0.
-TDC giving no signal: the new high resolution TDC board (1785) common stop (start?) has not been timed with respect to the inputs. So getting nothing out of the board is normal. The timing will be done once the triggers have been worked out : later.
-Cerenkov single rates: I did not realized that by design the discri is set very low, in order to maximize efficiency.
FIGURE 1
FIGURE 2
