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    User name A. Camsonne

    Log entry time 05:58:18 on February 19, 2011

    Entry number 347600

    keyword=Added initialization lines for TDC in ROC4 slot 23

    Bob noticed two lines missing in initialization for this TDC in sfi4.crl

    so I added those lines and recompiled the crl the secondary address 7 and write 2 :

    # Standalone TDC 1877 # Common stop, 1.5 microsec time window(0xbb), LIFO depth 6 # backplane gate

    geographic control TDC2SLOT write hex 40000000 secondary address 1 write hex 40000003 secondary address 18 write hex bb6 secondary address 7 write 2 release

    please redownload to see if that makes a difference while I am checking if the readout lines need to be modified for single module read, I guess it should be similar to 1875.



    A copy of this log entry has been emailed to: rom@jlab.org