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    User name R. Michaels

    Log entry time 08:30:32 on October 4,2000

    Entry number 49249

    This entry is a followup to: 49220

    keyword=timing adjustments (but not T0)

    Since we had changed T0 last night (halog 49204) we checked
    the ADC gates on R-arm, and they were ok. It seems this was
    because when we had originally set it up, we used 'nofpp' config
    which did not have the bit-error discovered yesterday. So, no T0 change.

    Re: the strange TCe:TCh picture in hana (halog 49230), this is
    understood, grimly. It happens because when T3 (L-arm) comes
    sufficiently early, T1 carries the coinc timing, and the retiming at
    the L-arm makes "forced gates". This is hard to understand without
    a picture, so I'll draw one in the paper log book. We did one thing:
    We reduced the width of the T3 signal to 20 nsec FWHM, which will
    do 2 things: 1) reduce the range of randoms to 70 nsec; and 2) reduce
    the range over which forced gates occur for T5 on L-arm. There's nothing
    we can do about the latter because of the "wall" of finite delay spools !!