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    User name atrig

    Log entry time 14:58:46 on January 3, 2001

    Entry number 53919

    keyword=tst_map
    #
    #	roc		(roc-name/number)
    roc	halladaq4	129.57.164.11
    #	CAMAC branch	Number of Crates
    camac	0		2
    #	(logical-name)	crate	slot	model		x-pos.	y-pos.
    Map
    # LEFT ARM SCINTILLATORS
    	s12L_l_disc	1       2       LeCroy4413	1	1
    	s12L_l_delay	1	4	LeCroy4418/16	2	1
    	s12L_logic	1	6	LeCroy4516	3	2
    	s12L_r_disc	1	14	LeCroy4413	1	3
    	s12L_r_delay	1	12	LeCroy4418/16	2	3
    	s12L_delay	1	8	LeCroy4418/16	4	2
    	s12L_mlu	1	10	LeCroy2373	5	2
    	stbL_delay1	1	16	LeCroy4418/16	3	3
    	stbL_delay2	1	17	LeCroy4418/16	4	3
    	stbL_logic	1	18	LeCroy4516	5	3
    	retimeL_logic   1       19      LeCroy4516      6       3
    #
    # LEFT ARM SINGLES, 2/3 TRIGGER, and LR COINCIDENCE
    	cherL_disc	2	2	LeCroy4413	1	5
    	cherL_delay	2	4	LeCroy4418/16	2	5
            mlu2L_delay     2       6       LeCroy4418/16   3       5
    	coinL_mlu	2	7	LeCroy2373	4	7
            LR_delay        2       9       LeCroy4518/300  5       7
    	L_delay_1       2       10      LeCroy4518/300  6       7
            LR_coin_logic   2       11      LeCroy4516      7       7
            Ltrig4_delay    2       13      LeCroy4418/16   5       9
            L_delay_2       2       14      LeCroy4518/300  8       7
    
    # LEFT ARM AEROGEL
    	aroL_l_disc	1	22	LeCroy4413	1	9
    	aroL_l_delay	1	23	LeCroy4418/16	2	9
    	aroL_r_disc	2	22	LeCroy4413	1	10
    	aroL_r_delay	2	23	LeCroy4418/16	2	10
    #
    Settings
    	s12L_l_disc	0	45
    	s12L_l_delay	0 5 0 5 5 5 0 5 0 5 5 5 5 5 5 5
    	s12L_logic	and-or
    	s12L_r_disc	0	45
    	s12L_r_delay	0 5 0 5 5 5 0 5 0 5 5 5 5 5 5 5
    	s12L_delay	0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
    	s12L_mlu	mode 	pulse
    	s12L_mlu	data 	mlu1_scint.data
    	stbL_logic	or-or
    	stbL_delay1	15 15 15 15 15 15 0 0 0 0 0 0 0 0 0 0
    	stbL_delay2	12 12 12 12 12 12 4 4 4 4 4 4 4 4 4 4
    	cherL_disc	0	30
    	cherL_delay	1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
    	coinL_mlu	mode 	tran
    	coinL_mlu	data 	mlu2_left.data
            LR_delay        0 8 8 0 0 0 0 0 0 0 0 0 0 0 0 0
    	L_delay_1       96 80 0 0 96 0 0 0 0 0 0 0 0 0 0 0
    	LR_coin_logic   and-or
    	Ltrig4_delay    15 15 15 15 15 15 15 15 15 15 0 0 0 0 0 0
    	L_delay_2       128 0 0 10 208 56 0 0 0 0 0 0 0 0 0 0
    	aroL_l_disc	0	60
    	aroL_l_delay	0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
    	aroL_r_disc	0	60
    	aroL_r_delay	0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0