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    User name R. Michaels

    Log entry time 14:44:38 on April21,2001

    Entry number 60968

    Followups:

    keyword=gate retiming for T2,T4 marginal

    On the way home I realized that the retiming for T2 and T4
    was not adjusted. Result would be a "forced" gate which is
    about 75 nsec late, a bit marginal for ADCs. I think this may
    not happen for T4 actually, but definitely for T2. If its a prob-
    lem I can come in and try to adjuste it (remove some cables).