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    User name gilman

    Log entry time 21:16:13 on July17,2001

    Entry number 66525

    This entry is a followup to: 66513

    keyword=helicity signals II



    While there is no evidence for "massive" 10^-3 asymmetries,
    we did observe a possible 10^-6 problem.

    If one looks at the "66" ms long helicity pusles, about one
    pulse every several seconds to perhaps one minute would have a
    glitch; in the center of the pulse, the phase with the "true" level
    would shift to "false" for ~ 25-50 ns, and the phase with the
    false level would simulateously shift to true for a similar time.
    These glitches seemed to happen more when the "-" phase
    was true, and the "+" phase was false. In discussions with
    Jack Segal, such glitches might arise, e.g., due to cross talk
    in Phillips level shifters. At this point we do not know if this
    glitch reflects any helicity changes for the beam.

    Assume that "+" phase is true and "-" phase is false when a glitch
    occurs. The glitch is long enough that the latch on the "+" phase
    is cleared, putting the system into "helicity 0" status for 500 us,
    while both delays run (offset by 25 - 50 ns, which we shall ignore).
    At the end of the 500 us, the "+" phase will be set to true again.
    For the "-" phase at the end of the 500 us delay,
    there is already a stop/reset signal present when the 500 us delayed signal
    tries to start/trigger the latch. The question is what happens.

    We could not test the Phillips 794 (used in left arm) in this case,
    because there were no spare modules available in counting house.
    For the LeCroy 222 (used in right arm), we set up a test in the
    counting house, there is a ~10-15 ns long true output!

    In the right arm, this will lead to no noticeable charge/time asymmetry,
    but it could lead to the helicity 2 events we see. When there is a glitch,
    it is sufficient in length to saturate an ADC channel,
    20 ns * 1 V = 20 nC, vs ~ 500 pC full scale for the ADC. With ~ 100 ns
    ADC gates, events arriving within ~200 ns will get both helicity signals;
    at 2 kHz rate there is ~200 ns / 500 us ~ 0.4*10^-3 = 1/2500 probability of
    there being such an event. At one glitch per 10 (60) seconds, you see one
    helicity 2 event every 25000 s ~ one per shift (one every other day).
    This seems about the right rate. Since we have been seeing occasional
    helicity 2 events, perhaps this has been going on unnnoticed for years.
    (Again, not an explanation for the 10^-3 problem.)

    We still need to test the Phillips 794, and see how it responds.

    RG, with Jack Segal, Wolfgang Korsch, JP