Also, because the ADCs were timed in so that they arrive 20ns earlier relative to their gates than the TDC do to their gates, (I.e. if a TDC stop arrives 30 ns after the start, the corresponding ADC signal arrives 10 ns after its gate), the timing of ADC gates relative to TDC starts was moved 20 ns earlier. This means that the ADC gates were moved 40 ns earlier.
The following steps were done to make this change. First 32 ns was removed from the common delay before the ADC and TDC gates are split. Then 20 ns seconds was added to the TDC gate (This was done with a 6 ns cable and a switchable delay box set to 14 ns.). At this point, the 20 ns change in relative TDC/ADC time is done and the TDC gate shifted 12 ns earlier. The gates were then shifted an additional 8 ns ealier by shifting the T3 time earlier by 8 ns. This places T3 10 ns after T5 instead of 18 ns.
The current settings on the blue delay box are now: