Detector 1 discrimination circuit was modified to minimize timing walk. This was done by sending two copies of the analog signal into two discriminators, one set to -50 mV, the other set to -100 mV. The discriminated signals are then ANDed such that the output timing is that of the low-threshold pulse.
The bottom line is that the hardware threshold on detector 1 is -100 mV (but should have reduced time-walk). There will be a relative shift in the timing of this signal due to the extra logic involved.
The hardware threshold for detector 2 was confirmed to be -50 mV. No
changes were made to this detector relative to the earlier runs.
A copy of this log entry has been emailed to: feuerbac@jlab.org