User name R. Michaels
Log entry time 14:02:25 on August 6,2007
Entry number 208731
keyword=NaI gate for CSR
Here is how I compute the gate timing for the fastest ADC gate
we can make for the NaI detector of CSR.
The total gate time is the sum of three components
T_total = T_sd + T_ts + T_fg
T_sd = time from scintillator to discriminator = 57 nsec
T_ts = time from discrim. to Trigger Supervisor input = 117 nsec
T_fg = time to go through Trig. Super. and arrive at ADC = 86 nsec
Therefore T_total = 260 nsec.
The uncertainty in this is +/- 15 nsec, which can be reduced
with more measurements.
T_sd is irreducible unless you replace cables.
T_ts (117 nsec) involves:
Time from discrim. to NIM/ECL that feeds TS = 97 nsec
Propogation through NIM/ECL = 10 nsec
Cable to TS = 10 nsec
T_fg (86 nsec) involves:
Time to propogate thru Trig. Super. = 40 nsec
Time to get to NIM/ECL = 10 nsec
Propogation through NIM/ECL = 10 nsec (this could be eliminated)
Cable to Fastbus backplane = 16 nsec
Time to propogate along backplane to ADC = 10 nsec