The ROC5 warnings have been tracked down to the event counter on the QDCs not being reset before each run.
The event counter is 24 bits, which means we've been running out of bit space every 17 runs or so. For some reason, this event counter is not being reset with the routine:
c792Clear(iadc);
So... I've added another line to the crl (before each c792Clear):
c792p[iadc]->evCountReset = 1;
and added a somewhat informative comment next to it.
This was done just before run 3454.