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    User name V. Sulkosky

    Log entry time 18:05:06 on September 10, 2008

    Entry number 243059

    This entry is a followup to: 242871

    keyword=Re: L-HRS DAQ problems fixed

    Bob fixed the problem that for all triggers other than T3, the L-HRS
    gates are missing, although there is a L1A from the TS. The problem was
    traced to module that the L1A signal was going through before going into
    the TS. This module caused the L1A pulse width to become ~ 40 ns
    compared to the standard few us. Apparently the retiming module has a
    problem with a narrow gate. The signal is now coming from the BigBite
    weldment and going directly into the LHRS TS. The synch problem between
    BigBite and the left HRS should be resolved now.

    In the meantime, the gate for the ADC in slot 20 of ROC 4 was unplugged
    from the TS when we were working on the gate problem yesterday. This
    caused ROC 4 to hang up and produce a 50% deadtime and no readout of the
    TDCs. This ADC was used for the CSR experiment, but is no longer
    in use. However the ADC is still in the readout and receives it's gate
    from the card's back panel. Hence ROC 4 was waiting on an ADC gate that
    never arrived.


    A copy of this log entry has been emailed to: kalyan@jlab.org,ycwang@jlab.org.xqian@jlab.org