Make New Entry, Make Followup Entry
User name camsonne / cisbani / wang
Log entry time 19:34:05 on November 13, 2008
Entry number 248681
This entry is a followup to: 248383
keyword=RICH activity during Nov/13/2008 accessList of open problems likely fixed during access
- Strange "pile-up" in cluster map
- Bad quality pedestal (possibly related to the previous)
- Missing strips in panel4 and 5 of mips map
We probably solved all of them, and found a new one (possibly relatively marginal) bug.
Timing double check
Double check trigger timing, attached new updated and more detailed timing diagram.CLEAR AFTER T/H Reset Added
Found missing gassiplex clear after T/H reset; added.This may explain the pileup in the last clust.x/y maps: each T3 open the T/H. when this is reset (T3 do not pass the prescale), the gassiplex hold circuit retains the charge if not cleared.
The new signal is ORed with the clear at the end of the T/H. At the moment the widths of the two clears are different: 75 ns (reset/clear) and 150 ns (end of t/h clear). Moreover, the clear NIM signal that goes to the gassiplex has a very short (1-2 ns) follower pulse. The problem seems in the last fan out. Funcionality should be not affected.
Pedestal/Noise issue
In the last pedestals we oberved an increasing noise going from the first to the last channels of each ADC. This is related to a wrong synch between clock and convert.The synching check done at the oscilloscope (looking at the ADC input and the convert signal) did not seem to work. We therefore performed a TS (phase between clock and convert) scan at two different clock frequencies (first 1000 events good for pedestal, then TS changed):
- 1.0 MHz: runs 3361 to 3366 contains the pedestals (except the first adc, used on the oscilloscope to set TS) corresponding to TS=0,...500 ns (step of 100 ns). In runs 3363 and 3364 (TS=100,200 ns) pedestals look excellent < 2 (excepts some channels in panel 2 see later).
- 1.775 MHz: runs 3367 to 3371, corresponding to TS=0 to 200 (step of 50 ns). Best pedestals for TS=100-150 ns.
NOTE: the sequencer on the ROC14 crate has a faulty TS adjustment screw. We therefore moved the READEVT, the CONVERT and the CLOCK logic to the sequencer in the CRATE of ROC15
Second panel pedestal/noise fluctuation
The noise of pedestals of panel 2 fluctuate in a original manner (respects to the other panels, as shown in attchament 2). We checked the clock cable at it looks fine. It could be the receiver (or transmitter) boards. The maximum noise it still reasonable (around 4ch) and therefore e do not proceed further right now.Missing strips in mips map
We found two cables connecting the gassiplex-out with the ADC-intput, in the wrong order. We swapped them. This certainly explains the missing two strips in the mips plot as a problem of wrong mapping; old data can be reprocessed with the proper mapping (swapping ADC14/ROC15 and ADC16/ROC15 ). From now on, the mapping is as it should be: ADC14 connected to panel3/row5 and ADC16 to panel4/row1Partial To Do List
- Take one pedestal before starting production
- Get beam data and analyze maps (mips and cluster)
- Investigate the above noise in second panel
- Perform the following scan, with beam (always RICH pedestal before data taking!):
- Do a HV scan (between 2100 to 2300 HV)
- Do a Thr scan (from 1. to 5. sigma)
- Do a Delay scan of the T/H respect to the T3
- Characterize the RICH performance
Fig1: RICH TIMING Updated
rich_timing_13nov08.pdfFig2: Pedestals and noise
