If a T1 is not present (ie. T3, T4, etc) then the retiming circuit will "time-out" after a few hundred nano-seconds and generate a gate timed off the L1A for the BB electronics. Double pulsing of the retiming circuit (due to multiple T1s) is removed with a self-timed veto.
Here's the snag.
T6 is a valid single arm trigger, but it was no obvious way for us to guarantee correct retiming for the case where there is a T6 but no T1. Right now the retiming circuit does not take T6 into account. As long as the threshold on T6 is greater then the threshold for T1, every T6 should also generate a T1 and everything will work as expected. If there is only a T6 but NO T1 (noise, relative thresholds are flip-flopped, gremlins), then the retiming circuit will time out and generate an ADC gate with the wrong timing.
Again, for the current configuration every T6 should also be a T1 since the T1 threshold is smaller, so the ration of 'lost' T6-only:T6+T1 triggers should be very small. This needs to be checked.
T2 is built using T6 and has the same caveats.
T7 is not useful right now. Don't worry about it.
We'll give the circuit some more thought and may fix these limitations
later, but not tonight.
A copy of this log entry has been emailed to: kalyan