Log entry time 14:43:41 on May19,2009

Entry number 274791

This entry is a followup to: 274757

Followups:

• 275271 05/21/09 09:45 X. Zheng access activity [PVDIS work]

1. Removed 16 ns delay from the veto for group5 to group8.

2. Defined tagger as 100 Hz pulser ORed with T1. But here is a 

   double standard: tagger for veto-part is only 100 Hz pulsar while

   the tagger for rest of the system is 100 Hz pulser ORed with T1.

3. Removed tagger input from the module which used to have tagger        ORed with PVDIS signal while forming the circuitry to produce TDC     inputs for pileup and "TDC dead-zone" spectra. Since we already       have tagger in the PVDIS inputs in TS-part of the flow-chart          diagram of PVDIS DAQ, its a mistake to OR this tagger again.