Though I saw there was still a block read of TDCSLOT1 so that might make weird data in the stream since the module is not initialized.
Though I tried to comment the read in the crl, but that did not fix the warning. I will look at it more tomorrow during the access.
Data for right arm looks reasonable so I leave the crl as it is right now.
A copy of this log entry has been emailed to: rom@jlab.org,moffit@jlab.org,vasulk@jlab.org,bozhao@jlab.org