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User name R. Michaels
Log entry time 12:40:58 on August29,2009
Entry number 286824
keyword=18-bit developments in test cage
Working in the test cage I've implemented improvements to the
handling of the VME state-machine of the 18-bit ADCs.
Full details are in ~apar/dev_bob/adc18_sum.txt (ASCII).
This appears to solve all problems, which were all related:
-- no deadtime
-- no "bad" flags
-- no scrambling of the order
-- the buffer is never full
It turns out that the data we've taken so far is ok (as far as
I've spot-checked it). I've developed some rapid code to diagnose
I want to put all the ADCs in the test cage through high-statistics
tests. After checking all channels for several oversampling factors
etc, we may "roll out" the new code for the experiment. I expect
to do this Sunday owl unless someone wants to stop me.
The old code will, of course, be saved.
Below is a snapshot of results for one ADC for the cases of
no-oversampling, OS by 4, and OS by 10.