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User name R. Michaels
Log entry time 04:28:22 on August30,2009
Entry number 286996
keyword=ADC18 Test Crate study (Part I)
As I said at around 2 pm, the ADC18 readout code was modified
to have a correct deadtime logic. I've been testing a crate with
four ADCs in the Test Crate.
Here in Part I, an anomoly observed with oversampling runs is shown.
The Peak may get a "glitch". These occur in all channels of all
4 ADCs simultaneously. I think the problem is a little different
from the peculiarity Kent showed in halog 286945 in that:
1. The CSR bits are all normal.
2. More than just one ADC is affected (some common origin)
3. I didn't see this in non-oversampling (several runs).
Not sure what to do about it now.