ROC31 works again after mysterious sequence

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User name R. Michaels

Log entry time 15:52:23 on October 21, 2009

Entry number 296007

This entry is a followup to: 295983

keyword=ROC31 works again after mysterious sequence

Tried the following tests on ROC31, per discussion with Paul King.
The "bottom line" is that after all this I restored the normal config
and it worked again. Tres bizarre. But maybe dropping all devices
and putting it back in shook something up ?

1. Drop the STR7200 scaler. This is done by setting nscalers_misc = 0 in
the CRL. Still have nscaler=1 and nadc=12. Result: ROC31 still crashes

2. In addition to no STR7200, set nscaler=0 and nadc=0 in g0inj.flags.
ROC31 runs. Ok, but no data.

3. Put back STR7200 (nscalers_misc = 1). Run with nscaler=0 and nadc=1.
Result: ROC31 runs.

4. nscaler_misc=1, nscaler=1, nadc=1. Result: ROC31 runs.

5. nscaler_misc=1, nscaler=1, nadc=6. Result: ROC31 runs (??!!)
(Reminder, we ran previously with nscaler=0 and nadc=6 and it
crashed. So it's not reproducible or I made a mistake. I did check
the printouts at vxWorks.)

6. Go for gold: nscaler_misc=1, nscaler=1, nadc=12 (normal config).
Result: ROC31 runs !!!!

Go figure. So maybe the algorithm is to temporarily drop all
devices (step 2) ?

Here is a printout on vxWorks to verify if I did the right thing
for the normal config (6th test):

------------- vxWorks dump for test 6 -------------------

daLogMsg: Entering User Prestart
daLogMsg: Reading flags from file
daLogMsg: Internal Config:
ffile=/adaqfs/halla/apar/g0inj/flags/g0inj.flags,badc=0xC1,nadc=3,vqwk
internal=0,vqwk_verbose=1
daLogMsg: rcDatabase Conf: g0inj
daLogMsg: Run time Config:
badc=0x80,nadc=12,nscaler=1,vqwkperiod=0,vqwkblocks=4,vqwksamples=4120
,vqwkdelay=20,vqwkinternal=2

Linking async VME trigger to id 1

disconnecting vector 236
daLogMsg: Begin setting up the JLab FlexIO module.
Initialized FlexIO at address 0x91000ee0
flexioPrintStatus: INFO: flexp->csr1 = 0xff48
flexioPrintID: INFO: port number 1 is an output card.
flexioPrintStatus: INFO: flexp->csr2 = 0xff9b
flexioPrintID: INFO: port number 2 is an input card.
flexioPrintStatus: INFO: flexp->data1 = 0x0000
flexioPrintStatus: INFO: flexp->data2 = 0x0011
flexioPrintStatus: INFO: flexp->interrupt = 0xff00
daLogMsg: Begin setting up the beam scalers.
daLogMsg: Initializing 1 scalers starting at addr_beam
0x0038d000
scslIntInit: scalInt is Connect. 0
sis3801InitializeMany: SIS3801 module 1 at addr=0x9038d000 initialized.
daLogMsg: Beam scalers initialized and cleared
daLogMsg: Begin setting up the VQWK modules.
daLogMsg: Set up 12 ADCs beginning with ladd 0x00800000 with address
steps of
0x00010000
vqwkInit: Initialized ADC ID 0 at address 0x90800000 with default parameters
The sample period is 40 clock cycles (register=0x0).
The number of blocks is 4.
The number of samples per blocks is 4120.
The acquisition will begin 20 clock cycles after the gate.
Internal gate frequency = 0.030303 kHz (register=0xce4).
Using INTERNAL 20 MHz CLOCK.
Using EXTERNAL GATE.
vqwkInit: Initialized ADC ID 1 at address 0x90810000 with default parameters
The sample period is 40 clock cycles (register=0x0).
The number of blocks is 4.
The number of samples per blocks is 4120.
The acquisition will begin 20 clock cycles after the gate.
Internal gate frequency = 0.030303 kHz (register=0xce4).
Using INTERNAL 20 MHz CLOCK.
Using EXTERNAL GATE.
vqwkInit: Initialized ADC ID 2 at address 0x90820000 with default parameters
The sample period is 40 clock cycles (register=0x0).
The number of blocks is 4.
The number of samples per blocks is 4120.
The acquisition will begin 20 clock cycles after the gate.
Internal gate frequency = 0.030303 kHz (register=0xce4).
Using INTERNAL 20 MHz CLOCK.
Using EXTERNAL GATE.
vqwkInit: Initialized ADC ID 3 at address 0x90830000 with default parameters
The sample period is 40 clock cycles (register=0x0).
The number of blocks is 4.
The number of samples per blocks is 4120.
The acquisition will begin 20 clock cycles after the gate.
Internal gate frequency = 0.030303 kHz (register=0xce4).
Using INTERNAL 20 MHz CLOCK.
Using EXTERNAL GATE.
vqwkInit: Initialized ADC ID 4 at address 0x90840000 with default parameters
The sample period is 40 clock cycles (register=0x0).
The number of blocks is 4.
The number of samples per blocks is 4120.
The acquisition will begin 20 clock cycles after the gate.
Internal gate frequency = 0.030303 kHz (register=0xce4).
Using INTERNAL 20 MHz CLOCK.
Using EXTERNAL GATE.
vqwkInit: Initialized ADC ID 5 at address 0x90850000 with default parameters
The sample period is 40 clock cycles (register=0x0).
The number of blocks is 4.
The number of samples per blocks is 4120.
The acquisition will begin 20 clock cycles after the gate.
Internal gate frequency = 0.030303 kHz (register=0xce4).
Using INTERNAL 20 MHz CLOCK.
Using EXTERNAL GATE.
vqwkInit: Initialized ADC ID 6 at address 0x90860000 with default parameters
The sample period is 40 clock cycles (register=0x0).
The number of blocks is 4.
The number of samples per blocks is 4120.
The acquisition will begin 20 clock cycles after the gate.
Internal gate frequency = 0.030303 kHz (register=0xce4).
Using INTERNAL 20 MHz CLOCK.
Using EXTERNAL GATE.
vqwkInit: Initialized ADC ID 7 at address 0x90870000 with default parameters
The sample period is 40 clock cycles (register=0x0).
The number of blocks is 4.
The number of samples per blocks is 4120.
The acquisition will begin 20 clock cycles after the gate.
Internal gate frequency = 0.030303 kHz (register=0xce4).
Using INTERNAL 20 MHz CLOCK.
Using EXTERNAL GATE.
vqwkInit: Initialized ADC ID 8 at address 0x90880000 with default parameters
The sample period is 40 clock cycles (register=0x0).
The number of blocks is 4.
The number of samples per blocks is 4120.
The acquisition will begin 20 clock cycles after the gate.
Internal gate frequency = 0.030303 kHz (register=0xce4).
Using INTERNAL 20 MHz CLOCK.
Using EXTERNAL GATE.
vqwkInit: Initialized ADC ID 9 at address 0x90890000 with default parameters
The sample period is 40 clock cycles (register=0x0).
The number of blocks is 4.
The number of samples per blocks is 4120.
The acquisition will begin 20 clock cycles after the gate.
Internal gate frequency = 0.030303 kHz (register=0xce4).
Using INTERNAL 20 MHz CLOCK.
Using EXTERNAL GATE.
vqwkInit: Initialized ADC ID 10 at address 0x908a0000 with default parameters
The sample period is 40 clock cycles (register=0x0).
The number of blocks is 4.
The number of samples per blocks is 4120.
The acquisition will begin 20 clock cycles after the gate.
Internal gate frequency = 0.030303 kHz (register=0xce4).
Using INTERNAL 20 MHz CLOCK.
Using EXTERNAL GATE.
vqwkInit: Initialized ADC ID 11 at address 0x908b0000 with default parameters
The sample period is 40 clock cycles (register=0x0).
The number of blocks is 4.
The number of samples per blocks is 4120.
The acquisition will begin 20 clock cycles after the gate.
Internal gate frequency = 0.030303 kHz (register=0xce4).
Using INTERNAL 20 MHz CLOCK.
Using EXTERNAL GATE.
vqwkInit: 12 ADC(s) successfully initialized
daLogMsg: VQWK ADCs initialized
daLogMsg: Begin setting up the miscelaneous scalers.
daLogMsg: Initializing 1 scalers starting at addr_misc
0x00c00000
first res = 0
second res = 0
Initialized Scaler ID 0 at address 0x90c00000
Scaler STR7200[0] started
daLogMsg: Miscelaneous scalers initialized and cleared
daLogMsg: Prestart Executed
informEB: msgQSend done...
daLogMsg: prestarted
daLogMsg: activating
informEB: msgQSend done...
rolp->daproc = 5
daLogMsg: Entering User Go 2
rolp->daproc = 5
daLogMsg: Entering Go
daLogMsg: Sending enable to the scalers during go
daLogMsg: Sending a disable to the STR7200 mask pattern 0xfffefcf0
daLogMsg: Send a disable signal to the VQWK ADC gates during go
daLogMsg: Clear the ADCs during go
daLogMsg: Setting gateflag to 2 and clockflag to 0.
daLogMsg: active, events so far 0 token 0
nevents 0 newevnb 256 old 119