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    User name Kai Pan

    Log entry time 23:04:03 on November 07, 2009

    Entry number 298188


    keyword=PVDIS DAQ: delay timing, discriminator threshold, width

    1. Now all 6 groups on left arm were added 113~116 ns delayed cables. 2. discriminator threshold: Left: H:65,M:25,L:20 Right: H:90, M:20, L:20 3. discriminator width: previously, the narrow on left arm is set to 60ns due to the deadtime test before happex. I restore all narrow to be 30ns now. All wide were 100ns already. Right arm is 30ns in narrow and 100ns in wide already. 4. I found that on right arm shower sum8 of group2, there is one unterminated output channel which caused many jitters when I was checking the offset of TS analog sum. Problem fixed.

    A copy of this log entry has been emailed to: xiaochao, rom, rsubedi, pkpan