Expanded ADC gate from 300 ns to 400ns so as to cover all pion rejector signal inside the gate.
Found that the time between L1A and retiming fluctuating between 84 ns to 184 ns (retiming being late). Originally it was set as 56 ns. Not sure how it went that way. We did not change anything on this today though.
Fixed tagger signal in LHRS. It must be there now. At least we can see from scaler display.
Tracked down that the ribbon cable responsible for event-type-bits variables was still there in crate 4 slot 13 and channel 0-23 (it is a ribbon cable for 25 pins including a ground pin) and connected to the trigger supervisor. Its not clear why we do not see any event-type-bits histograms in the data.
Fixed BCM-d3 signal(probably loose cable). Now its there.
Fixed one of the pileup signals (probably loose cable), now its visible.
Found that the T1 signal going to the Trigger Supervisor was not there. While looking into the data that we took before the access, T1 is there. Looks like it became loose at the moment we were working there, it is fixed now anyways.