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User name R. Michaels
Log entry time 17:07:41 on June30,2010
Entry number 329213
This entry is a followup to: 329198
keyword=trig / daq status update
With a lot of work done by Neil and Kurtis, here's the status
The pulser goes on a cable from R-HRS to L-HRS which is 232 nsec
long, measured with reflections. The pulser on R-HRS is compensated
so the signals arrive at the S2m electronics at the same time.
Coinc of S2m on L and R-HRS:
The overlap at the coincidence circuit is good. Two signals 10 nsec
wide with the R-HRS late by 3 nsec.
The delay of T1 to TS (trig. super.) did not need to be adjusted,
though there was a slight complication that we had to bypass the
old route. So the gates on L-HRS should be good and unchanged.
The R-HRS trig. and coinc. trigger were lined up to match T1 at TS.
The triggers are
T1 = L-HRS S2m
T2 = L-HRS S0
T3 = R-HRS S2m
T4 = coincidence of T1 and T3
T5 = L-HRS singles from a coinc of S0 and GasCer.
T6 = T4.and.GasCer on R-HRS (added later, see halog 329311).
T8 = 1024 Hz pulser
T1, T2, T5, and T8 were not changed from previous running.
A "to do" list which I think takes 5 hours:
1. Some fine-tuning of the alignment of timing at TS.
2. Scope checks of gate timing (repeat L-HRS, do the R-HRS 1st time)
3. Put all triggers into a TDC to measure coinc. time.
4. Use front-panel gates for ADCs on R-HRS (presently back-panel).
5. Finish scaler cabling.
6. Formation of the coinc trigger S2m-L.and.S2m-R.and.GasCer-R
7. Fix / replace the TDC in ROC1 slot 11 (separate halog entry).
I think the timing on R-HRS may be good enough for VDC checkout.