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    User name A. Camsonne

    Log entry time 19:39:11 on October 21, 2010

    Entry number 336040

    This entry is a followup to: 336037

    Followups:

    keyword=DVCS Logic module

    There might have been changes in the timing of the generation of the T5 while we were fixing the scalers output. So we might be able to solve the issue remotely in the FPGA. We will try to restore the previous timing and see if the HRS data looks ok.