trigger timing checks

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User name Bob/Alex/Hisham

Log entry time 01:14:03 on December11,2010

Entry number 343711

keyword=trigger timing checks

Work done by Alexander, Hisham and Bob

Since the improved ARS trigger board produces a further delayed
trigger, all gates were too late by 60 nsec. We did the following

1. ADC gates come directly from TS to backplane of ROC3, ROC4.
2. TDC1875 stop (data) signals will be delayed by ~60 nsec

Trigger work
S2m delayed by 48 ns
Gas Cerenkov delayed by 32 ns

All signal in the gates wthat analog signal about 80 ns after the beginning of the gate for trigger width 15-> 75 ns besides pion rejector ( 100 ns ? ), I might want to make a gate from L1A for this one I will think about it and doublec check it.

Checked retiming L1A was arriving 80 ns after retiming, I added some delay on RT to make sure we don't have forced retiming. Not ideal but should be good for testing the trigger