After this adjustment, the retiming(strobe) delay is about 640ns,which is directly from the S1.or.S2m Logic module to retiming module (LEMO input). And delay of L1A to retiming module is about 510 ns. This time I adjusted the ADC signals and its gate very carefully and new they are about ~60ns in between. I hope this time the data would looks better. The distance between TDC stop signal and TDC signals when using 1877, is about 800ns for S2m and 760ns for S1, which means that if we need to use 1875 TDC, which requires 200ns later than TDC start for TDC signals, we need to delay the TDC signals about 1000ns before sending them into Fast Bus. I start a new long run(#20065) with cosmic ray.