Fastbus sync check clock

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User name A. Camsonne

Log entry time 19:07:00 on February 17, 2011

Entry number 347378

keyword=Fastbus sync check clock

I readded the loading of the scaler library from ~a-onl/scaler/scaroc

at boot for all the fastbus crate and modified the crl so the clocks get
read out.

The cabling is 

all channels starts at 0

ROC1 CAEN 560 channel 8
ROC2 Lecroy 1151 channel 15
ROC3 Lecroy 1151 channel 0
ROC4 Lecroy 1151 channel 0

the clocks are read as time2 and inserted after the header 0xfabc0006 6th
word.

It will be good to do a soft reboot of the fastbus crate to make sure all
libraries are loaded correctly and the crl were modified correctly.
So please do that when you have a minute.

A copy of this log entry has been emailed to: rom@jlab.org,vasulk@jlab.org,lselvy@jlab.org,danez@jlab.org,yez@jlab.org