Log entry time 13:15:30 on March 01, 2011

Entry number 349382

Followups:

• 349386 03/01/11 13:24 lselvy ROC 1 adn 2 CRL code
• 349388 03/01/11 13:36 lselvy Major revision to crl code for Rocs 1 and 2
• 349410 03/01/11 15:35 lselvy Reverted CRL code for ROC 1 and 2 back

The problems with ROC 1 and 2 not reading out the ADCs during a pedestal
run is still ongoing.

The culprit seems to be antiquated code dealing with excluding a specific
event type from readout.  Minor modifcations to this code have yileded no
change in the data from the pedesal runs.

The code in sfi1 and 2 crl that is the culprit is as follows:
if (event_ty != NEXTEVT) {

    *rol->dabufp++ = 0xdc0000ff;

/* Now clear bump the event pointers of all the modules that
   did get a gate so that we do not get out of sync  */

    if(datascan & (1