Log entry time 17:52:28 on March 16, 2011

Entry number 352164

This entry is a followup to: 352159

Followups:

• 352166 03/16/11 18:17 igorko ADCs gate

I see two issues here.

The cut-off at channel -500 could be due to several things.

• It could be one edge of the programmed F1 TDC window. Whether it is the start or end of the window depends on how the data in the plot show have been processed. (Ie. does the time axis run right to left, or left to right?) It would also be easy to have Steve or another expert tweak the lookback window size and offset to test this.
• -500 in this plot could correspond to 0 before some global offset is applied. If there is a 500 bin offset being applied in the F1 TDC database files then some part of the code probably throwing data <=0 as being 'non-physical'. Given how sharp the edge is, I suspect it is something like this.

I am actually more puzzled/concerned by the "double gate" structure I've high-lighted in the figure. It looks like the length of the ADC gate is alternating between ~300 bins and something ~550 bins. (Is 1bin == 1ns?). Do you know what the ADC gate width should be? How does it compare to what you measure off this plot? Perhaps this is an indication of a double pulse hitting an 'updating'-type logic module that is generating the gate. Since the ADC gate derives from the L1A, and there should only be one L1A per trigger (or things break), this could indicate a problem.

I can also think of ways that the retiming circuit on the BB arm could do this, particularly if the ADC gate is being fed directly from the retiming module output, rather than being formed by a 'dedicated' logic unit. The dedicated logic that used to set the ADC width may have been removed in order to make sure the gate made it to the ADCs before the signals...

Figure 1