Author: Xin & Kalyan 1. Understand DDB.t3[0]: This is a FASTBUS COMMON STOP TDC, so large channel means larger gap, smaller channel means smaller gap T->Draw("DBB.t3[0]","DBB.edtpr==0&& DBB.evtypebits&(1<<3)") (Figure 1) There are three regions: 1.1 Region I , DBB.t3[0]>643 this is when BB retiming not working 1.2 Region II, 173<DBB.t3[0]<643 this is when BB retiming working 1.3 Region III, DBB.t3[0]<173, this is when L1A steals BB retiming This is an imporant thing, since only region II gives the good data! Try to plot ADC vs TDC for signals in all three regions. ADC is only working good in Region II (since it is self triggering) ADC is not working in Region I and Region III. Try to plot ADC vs TOF in all three regions. Figure 8 and neutro_time.C 2. Understand BB.tp.e.tof[] T->Draw("DBB.t3[0]:BB.tp.e.tof","DBB.edtpr==0&& DBB.evtypebits&(1<<3)&&BB.tp.e.tof>-1000") (Figure 2) There are a gap, and a line Line: BB signal, BB trigger, so self timing Gap: Bias due to BB signal, The existance of BB signal tells us that there is no signal before that. So from this figure that we know left of BB.tp.e.tof is EARLY!!! It is fine to understand why the gap is just like that! Try to figure it out ... (240 channels for L1A-L1ADm, 150 channels for BB width, 390 = L1A-L1ADm + BB width) 3. What is coincidence timing? Answer 0.5*DBB.t3[0] + BB.tp.e.tof Why? DBB.t3[0]: L1A - Stop (large channel, further apart) BB.tp.e.top: -(BB - Stop) ( large negative value, further apart) factor 0.5 : is to adjust TDC resolution 4. Old Run: compare to New Run Figure 3. 5. New Run: (before adjust 20 ns , make L1A from Left HRS a little bit earlier) Figure 4. 6. Coincidence Timing in Neutron Arm. (Old Run) T->Draw("NA.tr.tof[]","DBB.edtpr==0&& DBB.evtypebits&(1<<3)&&NA.tr.tof[]<3000."); (Figure 5) Coincidence peak at about 82 channel 7. Coincidence Timing Neutron Arm (New Run) Figure 6. ~60 ns, about 20 ns shift. 8. Neutron Arm Time Walk ADC vs. TDC T->Draw("NA.tr.energy:NA.tr.tof>>(150,-500,1500,100,0,3000)","DBB.edtpr==0 && DBB.evtypebits&(1<<3) && abs(L.gold.dp)<0.045","colz"); Figure 7: ADC vs. TDC. Gate is kind of late for signal. (combine 7. and 8.)
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