Log entry time 11:19:54 on March 31, 2011

Entry number 353885

This morning when Vince modified CRL code, we found that in the code, the
ADC gates are still provided by signals from back panel of the fast bus
crate, which is the same as TDC STOP signals, although we provide gates
signals into the front panels of ADC cards.

The signals of ADC gates and TDC STOP are basically from the same source
at TM, but ADC gates signals go through several modules and are splitted
into five copies before they are sent into ADC modules in ROC3&4. I only
checked the ADC signals with ADC gate that go to the front. 

However, the width of ADC gates are set to be 270ns, so even the ADC
gates signals are delayed by up to 70ns by comparing with TDC STOP (which
should be much less since they only go through 2 or 3 modules),or saying,
the actual ADC gates now is the same as TDC STOP which comes earlier, we
still have at least 200ns width for ADC signals.

We have not seen any problem with ADC distribution of detectors (except
Cerenkove ADC, which is another story) so we might can leave it like this
way.