The wire plot, gate for each wire, tdc for each module are displayed.
U1_M11 module is missing. U3_M5_B subgroup is missing. This is possible electronics problem.
For U3 wire 40-48, couple of wires are missing. This is because of M3_B8(40), M3_A3(43), M3_A6(46) ,M3_A8(48) wires are removed.
The gates have been calibrated.
The tdc plots show there is a bump before the peak for some modules, which is due to different triggering.
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Figure 13