Subject: Re: Channel list for iocha17. Date: Mon, 02 Apr 2001 10:23:32 -0400 From: Pamela Kjeldsen To: segal Jack, Here are the rest of the files. Pam segal wrote: > Pam, > Could you send me a list of the channels in the iocha17 > database (Hall A Gas Shed)? I seem to have the name of one > or two channels wrong. Actually, if you could send me a list > for each of the iocs? Or post them somewhere I can find them? > -- > John Segal > Hall A Detector Systems Coordinator > Thomas Jefferson National Accelerator Facility M.S.90C > 12000 Jefferson Avenue > Newport News, VA 23606 > Phone: (757) 269-7242 -- Pamela S. Kjeldsen Address: TJNAF/Mailstop 85 Phone: 757-269-7066 12000 Jefferson Ave. Pager: 757-849-7066 NN, VA. 23608 Email: kjeldsen@cebaf.gov --------------------------------------------------------------------- # # Signal | Card | Sgn | #--------------------------|------|-----| HRSE_DTECTR_VMIC1182:0_Ch0 0 0 HRSE_DTECTR_VMIC1182:0_Ch1 0 1 HRSE_DTECTR_VMIC1182:0_Ch2 0 2 HRSE_DTECTR_VMIC1182:0_Ch3 0 3 HRSE_DTECTR_VMIC1182:0_Ch4 0 4 HRSE_DTECTR_VMIC1182:0_Ch5 0 5 HRSE_DTECTR_VMIC1182:0_Ch6 0 6 HRSE_DTECTR_VMIC1182:0_Ch7 0 7 HRSE_DTECTR_VMIC1182:0_Ch8 0 8 HRSE_DTECTR_VMIC1182:0_Ch9 0 9 HRSE_DTECTR_VMIC1182:0_Ch10 0 10 HRSE_DTECTR_VMIC1182:0_Ch11 0 11 HRSE_DTECTR_VMIC1182:0_Ch12 0 12 HRSE_DTECTR_VMIC1182:0_Ch13 0 13 HRSE_DTECTR_VMIC1182:0_Ch14 0 14 HRSE_DTECTR_VMIC1182:0_Ch15 0 15 HRSE_DTECTR_VMIC1182:0_Ch16 0 16 HRSE_DTECTR_VMIC1182:0_Ch17 0 17 HRSE_DTECTR_VMIC1182:0_Ch18 0 18 HRSE_DTECTR_VMIC1182:0_Ch19 0 19 HRSE_DTECTR_VMIC1182:0_Ch20 0 20 HRSE_DTECTR_VMIC1182:0_Ch21 0 21 HRSE_DTECTR_VMIC1182:0_Ch22 0 22 HRSE_DTECTR_VMIC1182:0_Ch23 0 23 HRSE_DTECTR_VMIC1182:0_Ch24 0 24 HRSE_DTECTR_VMIC1182:0_Ch25 0 25 HRSE_DTECTR_VMIC1182:0_Ch26 0 26 HRSE_DTECTR_VMIC1182:0_Ch27 0 27 HRSE_DTECTR_VMIC1182:0_Ch28 0 28 HRSE_DTECTR_VMIC1182:0_Ch29 0 29 HRSE_DTECTR_VMIC1182:0_Ch30 0 30 HRSE_DTECTR_VMIC1182:0_Ch31 0 31 HRSE_DTECTR_VMIC1182:0_Ch31 0 32 HRSE_DTECTR_VMIC1182:0_Ch31 0 33 HRSE_DTECTR_VMIC1182:0_Ch31 0 34 HRSE_DTECTR_VMIC1182:0_Ch31 0 35 HRSE_DTECTR_VMIC1182:0_Ch31 0 36 HRSE_DTECTR_VMIC1182:0_Ch31 0 37 HRSE_DTECTR_VMIC1182:0_Ch31 0 38 HRSE_DTECTR_VMIC1182:0_Ch31 0 39 HRSE_DTECTR_VMIC1182:0_Ch30 0 40 HRSE_DTECTR_VMIC1182:0_Ch31 0 41 HRSE_DTECTR_VMIC1182:0_Ch31 0 42 HRSE_DTECTR_VMIC1182:0_Ch31 0 43 HRSE_DTECTR_VMIC1182:0_Ch31 0 44 HRSE_DTECTR_VMIC1182:0_Ch31 0 45 HRSE_DTECTR_VMIC1182:0_Ch31 0 46 HRSE_DTECTR_VMIC1182:0_Ch31 0 47 HRSE_DTECTR_VMIC1182:0_Ch31 0 48 HRSE_DTECTR_VMIC1182:0_Ch31 0 49 HRSE_DTECTR_VMIC1182:0_Ch30 0 50 HRSE_DTECTR_VMIC1182:0_Ch31 0 51 HRSE_DTECTR_VMIC1182:0_Ch31 0 52 HRSE_DTECTR_VMIC1182:0_Ch31 0 53 HRSE_DTECTR_VMIC1182:0_Ch31 0 54 HRSE_DTECTR_VMIC1182:0_Ch31 0 55 HRSE_DTECTR_VMIC1182:0_Ch31 0 56 HRSE_DTECTR_VMIC1182:0_Ch31 0 57 HRSE_DTECTR_VMIC1182:0_Ch31 0 58 HRSE_DTECTR_VMIC1182:0_Ch59 0 59 HRSE_DTECTR_VMIC1182:0_Ch60 0 60 HRSE_DTECTR_VMIC1182:0_Ch61 0 61 HRSE_DTECTR_VMIC1182:0_Ch62 0 62 HRSE_DTECTR_VMIC1182:0_Ch63 0 63 --------------------------------------------------------------------- Signal | Card | Sgn | --------------------------|------|-----| HacRICH_VMIC1182:0_Ch0 0 0 HacRICH_VMIC1182:0_Ch1 0 1 HacRICH_VMIC1182:0_Ch2 0 2 HacRICH_VMIC1182:0_Ch3 0 3 HacRICH_VMIC1182:0_Ch4 0 4 HacRICH_VMIC1182:0_Ch5 0 5 HacRICH_VMIC1182:0_Ch6 0 6 HacRICH_VMIC1182:0_Ch7 0 7 HacRICH_VMIC1182:0_Ch8 0 8 HacRICH_VMIC1182:0_Ch9 0 9 HacRICH_VMIC1182:0_Ch10 0 10 HacRICH_VMIC1182:0_Ch11 0 11 HacRICH_VMIC1182:0_Ch12 0 12 HacRICH_VMIC1182:0_Ch13 0 13 --------------------------------------------------------------------- # # Signal | Card | Sgn | #--------------------------|------|-----| HacH_DTC_VMIC1182:0_Ch0 0 0 HacH_DTC_VMIC1182:0_Ch1 0 1 HacH_DTC_VMIC1182:0_Ch2 0 2 HacH_DTC_VMIC1182:0_Ch3 0 3 HacH_DTC_VMIC1182:0_Ch4 0 4 HacH_DTC_VMIC1182:0_Ch5 0 5 HacH_DTC_VMIC1182:0_Ch6 0 6 HacH_DTC_VMIC1182:0_Ch7 0 7 HacH_DTC_VMIC1182:0_Ch8 0 8 HacH_DTC_VMIC1182:0_Ch9 0 9 HacH_DTC_VMIC1182:0_Ch10 0 10 HacH_DTC_VMIC1182:0_Ch11 0 11 HacH_DTC_VMIC1182:0_Ch12 0 12 HacH_DTC_VMIC1182:0_Ch13 0 13 HacH_DTC_VMIC1182:0_Ch14 0 14 HacH_DTC_VMIC1182:0_Ch15 0 15 HacH_DTC_VMIC1182:0_Ch16 0 16 HacH_DTC_VMIC1182:0_Ch17 0 17 HacH_DTC_VMIC1182:0_Ch18 0 18 HacH_DTC_VMIC1182:0_Ch19 0 19 HacH_DTC_VMIC1182:0_Ch20 0 20 HacH_DTC_VMIC1182:0_Ch21 0 21 HacH_DTC_VMIC1182:0_Ch22 0 22 HacH_DTC_VMIC1182:0_Ch23 0 23 HacH_DTC_VMIC1182:0_Ch24 0 24 HacH_DTC_VMIC1182:0_Ch25 0 25 HacH_DTC_VMIC1182:0_Ch26 0 26 HacH_DTC_VMIC1182:0_Ch27 0 27 HacH_DTC_VMIC1182:0_Ch28 0 28 HacH_DTC_VMIC1182:0_Ch29 0 29 HacH_DTC_VMIC1182:0_Ch30 0 30 HacH_DTC_VMIC1182:0_Ch31 0 31 HacH_DTC_VMIC1182:0_Ch31 0 32 HacH_DTC_VMIC1182:0_Ch31 0 33 HacH_DTC_VMIC1182:0_Ch31 0 34 HacH_DTC_VMIC1182:0_Ch31 0 35 HacH_DTC_VMIC1182:0_Ch31 0 36 HacH_DTC_VMIC1182:0_Ch31 0 37 HacH_DTC_VMIC1182:0_Ch31 0 38 HacH_DTC_VMIC1182:0_Ch31 0 39 HacH_DTC_VMIC1182:0_Ch30 0 40 HacH_DTC_VMIC1182:0_Ch31 0 41 HacH_DTC_VMIC1182:0_Ch31 0 42 HacH_DTC_VMIC1182:0_Ch31 0 43 HacH_DTC_VMIC1182:0_Ch31 0 44 HacH_DTC_VMIC1182:0_Ch31 0 45 HacH_DTC_VMIC1182:0_Ch31 0 46 HacH_DTC_VMIC1182:0_Ch31 0 47 HacH_DTC_VMIC1182:0_Ch31 0 48 HacH_DTC_VMIC1182:0_Ch31 0 49 HacH_DTC_VMIC1182:0_Ch30 0 50 HacH_DTC_VMIC1182:0_Ch31 0 51 HacH_DTC_VMIC1182:0_Ch31 0 52 HacH_DTC_VMIC1182:0_Ch31 0 53 HacH_DTC_VMIC1182:0_Ch31 0 54 HacH_DTC_VMIC1182:0_Ch31 0 55 HacH_DTC_VMIC1182:0_Ch31 0 56 HacH_DTC_VMIC1182:0_Ch31 0 57 HacH_DTC_VMIC1182:0_Ch31 0 58 HacH_DTC_VMIC1182:0_Ch59 0 59 HacH_DTC_VMIC1182:0_Ch60 0 60 HacH_DTC_VMIC1182:0_Ch61 0 61 HacH_DTC_VMIC1182:0_Ch62 0 62 HacH_DTC_VMIC1182:0_Ch63 0 63 --------------------------------------------------------------------- # # Signal | Card | Sgn | #--------------------------|------|-----| HRSE_DTECTR_VMIC2210:0_Ch0 0 0 HRSE_DTECTR_VMIC2210:0_Ch1 0 1 HRSE_DTECTR_VMIC2210:0_Ch2 0 2 HRSE_DTECTR_VMIC2210:0_Ch3 0 3 HRSE_DTECTR_VMIC2210:0_Ch4 0 4 HRSE_DTECTR_VMIC2210:0_Ch5 0 5 HRSE_DTECTR_VMIC2210:0_Ch6 0 6 HRSE_DTECTR_VMIC2210:0_Ch7 0 7 HRSE_DTECTR_VMIC2210:0_Ch8 0 8 HRSE_DTECTR_VMIC2210:0_Ch9 0 9 HRSE_DTECTR_VMIC2210:0_Ch10 0 10 HRSE_DTECTR_VMIC2210:0_Ch11 0 11 HRSE_DTECTR_VMIC2210:0_Ch12 0 12 HRSE_DTECTR_VMIC2210:0_Ch13 0 13 HRSE_DTECTR_VMIC2210:0_Ch14 0 14 HRSE_DTECTR_VMIC2210:0_Ch15 0 15 HRSE_DTECTR_VMIC2210:0_Ch16 0 16 HRSE_DTECTR_VMIC2210:0_Ch17 0 17 HRSE_DTECTR_VMIC2210:0_Ch18 0 18 HRSE_DTECTR_VMIC2210:0_Ch19 0 19 HRSE_DTECTR_VMIC2210:0_Ch20 0 20 HRSE_DTECTR_VMIC2210:0_Ch21 0 21 HRSE_DTECTR_VMIC2210:0_Ch22 0 22 HRSE_DTECTR_VMIC2210:0_Ch23 0 23 HRSE_DTECTR_VMIC2210:0_Ch24 0 24 HRSE_DTECTR_VMIC2210:0_Ch25 0 25 HRSE_DTECTR_VMIC2210:0_Ch26 0 26 HRSE_DTECTR_VMIC2210:0_Ch27 0 27 HRSE_DTECTR_VMIC2210:0_Ch28 0 28 HRSE_DTECTR_VMIC2210:0_Ch29 0 29 HRSE_DTECTR_VMIC2210:0_Ch30 0 30 HRSE_DTECTR_VMIC2210:0_Ch31 0 31 HRSE_DTECTR_VMIC2210:0_Ch32 0 32 HRSE_DTECTR_VMIC2210:0_Ch33 0 33 HRSE_DTECTR_VMIC2210:0_Ch34 0 34 HRSE_DTECTR_VMIC2210:0_Ch35 0 35 HRSE_DTECTR_VMIC2210:0_Ch36 0 36 HRSE_DTECTR_VMIC2210:0_Ch36 0 37 HRSE_DTECTR_VMIC2210:0_Ch36 0 38 HRSE_DTECTR_VMIC2210:0_Ch36 0 39 HRSE_DTECTR_VMIC2210:0_Ch36 0 40 HRSE_DTECTR_VMIC2210:0_Ch36 0 41 HRSE_DTECTR_VMIC2210:0_Ch36 0 42 HRSE_DTECTR_VMIC2210:0_Ch36 0 43 HRSE_DTECTR_VMIC2210:0_Ch36 0 44 HRSE_DTECTR_VMIC2210:0_Ch36 0 45 HRSE_DTECTR_VMIC2210:0_Ch36 0 46 HRSE_DTECTR_VMIC2210:0_Ch36 0 47 HRSE_DTECTR_VMIC2210:0_Ch36 0 48 HRSE_DTECTR_VMIC2210:0_Ch36 0 49 HRSE_DTECTR_VMIC2210:0_Ch36 0 50 HRSE_DTECTR_VMIC2210:0_Ch36 0 51 HRSE_DTECTR_VMIC2210:0_Ch36 0 52 HRSE_DTECTR_VMIC2210:0_Ch36 0 53 HRSE_DTECTR_VMIC2210:0_Ch36 0 54 HRSE_DTECTR_VMIC2210:0_Ch36 0 55 HRSE_DTECTR_VMIC2210:0_Ch36 0 56 HRSE_DTECTR_VMIC2210:0_Ch36 0 57 HRSE_DTECTR_VMIC2210:0_Ch36 0 58 HRSE_DTECTR_VMIC2210:0_Ch59 0 59 HRSE_DTECTR_VMIC2210:0_Ch60 0 60 HRSE_DTECTR_VMIC2210:0_Ch61 0 61 HRSE_DTECTR_VMIC2210:0_Ch62 0 62 HRSE_DTECTR_VMIC2210:0_Ch63 0 63 --------------------------------------------------------------------- # # Signal | Card | Sgn | #--------------------------|------|-----| HacRICH_VMIC2210:0_Ch0 0 0 HacRICH_VMIC2210:0_Ch1 0 1 HacRICH_VMIC2210:0_Ch2 0 2 HacRICH_VMIC2210:0_Ch3 0 3 HacRICH_VMIC2210:0_Ch4 0 4 HacRICH_VMIC2210:0_Ch5 0 5 HacRICH_VMIC2210:0_Ch6 0 6 --------------------------------------------------------------------- # # Signal | Card | Sgn | #--------------------------|------|-----| HacH_DTC_VMIC2210:0_Ch0 0 0 HacH_DTC_VMIC2210:0_Ch1 0 1 HacH_DTC_VMIC2210:0_Ch2 0 2 HacH_DTC_VMIC2210:0_Ch3 0 3 HacH_DTC_VMIC2210:0_Ch4 0 4 HacH_DTC_VMIC2210:0_Ch5 0 5 HacH_DTC_VMIC2210:0_Ch6 0 6 HacH_DTC_VMIC2210:0_Ch7 0 7 HacH_DTC_VMIC2210:0_Ch8 0 8 HacH_DTC_VMIC2210:0_Ch9 0 9 HacH_DTC_VMIC2210:0_Ch10 0 10 HacH_DTC_VMIC2210:0_Ch11 0 11 HacH_DTC_VMIC2210:0_Ch12 0 12 HacH_DTC_VMIC2210:0_Ch13 0 13 HacH_DTC_VMIC2210:0_Ch14 0 14 HacH_DTC_VMIC2210:0_Ch15 0 15 HacH_DTC_VMIC2210:0_Ch16 0 16 HacH_DTC_VMIC2210:0_Ch17 0 17 HacH_DTC_VMIC2210:0_Ch18 0 18 HacH_DTC_VMIC2210:0_Ch19 0 19 HacH_DTC_VMIC2210:0_Ch20 0 20 HacH_DTC_VMIC2210:0_Ch21 0 21 HacH_DTC_VMIC2210:0_Ch22 0 22 HacH_DTC_VMIC2210:0_Ch23 0 23 HacH_DTC_VMIC2210:0_Ch24 0 24 HacH_DTC_VMIC2210:0_Ch25 0 25 HacH_DTC_VMIC2210:0_Ch26 0 26 HacH_DTC_VMIC2210:0_Ch27 0 27 HacH_DTC_VMIC2210:0_Ch28 0 28 HacH_DTC_VMIC2210:0_Ch29 0 29 HacH_DTC_VMIC2210:0_Ch30 0 30 HacH_DTC_VMIC2210:0_Ch31 0 31 HacH_DTC_VMIC2210:0_Ch32 0 32 HacH_DTC_VMIC2210:0_Ch33 0 33 HacH_DTC_VMIC2210:0_Ch34 0 34 HacH_DTC_VMIC2210:0_Ch35 0 35 HacH_DTC_VMIC2210:0_Ch36 0 36 HacH_DTC_VMIC2210:0_Ch59 0 59 HacH_DTC_VMIC2210:0_Ch60 0 60 HacH_DTC_VMIC2210:0_Ch61 0 61 HacH_DTC_VMIC2210:0_Ch62 0 62 HacH_DTC_VMIC2210:0_Ch63 0 63 --------------------------------------------------------------------- # # Signal | Card | Sgn | #--------------------------|------|-----| HRSE_DTECTR_VMIC4140:0_Ch0 0 0 HRSE_DTECTR_VMIC4140:0_Ch1 0 1 HRSE_DTECTR_VMIC4140:0_Ch2 0 2 HRSE_DTECTR_VMIC4140:0_Ch3 0 3 HRSE_DTECTR_VMIC4140:0_Ch4 0 4 HRSE_DTECTR_VMIC4140:0_Ch5 0 5 HRSE_DTECTR_VMIC4140:0_Ch6 0 6 HRSE_DTECTR_VMIC4140:0_Ch7 0 7 HRSE_DTECTR_VMIC4140:0_Ch8 0 8 HRSE_DTECTR_VMIC4140:0_Ch9 0 9 HRSE_DTECTR_VMIC4140:0_Ch10 0 10 HRSE_DTECTR_VMIC4140:0_Ch11 0 11 HRSE_DTECTR_VMIC4140:0_Ch12 0 12 HRSE_DTECTR_VMIC4140:0_Ch13 0 13 HRSE_DTECTR_VMIC4140:0_Ch14 0 14 HRSE_DTECTR_VMIC4140:0_Ch15 0 15 HRSE_DTECTR_VMIC4140:0_Ch16 0 16 HRSE_DTECTR_VMIC4140:0_Ch17 0 17 HRSE_DTECTR_VMIC4140:0_Ch18 0 18 HRSE_DTECTR_VMIC4140:0_Ch19 0 19 HRSE_DTECTR_VMIC4140:0_Ch20 0 20 HRSE_DTECTR_VMIC4140:0_Ch21 0 21 HRSE_DTECTR_VMIC4140:0_Ch22 0 22 HRSE_DTECTR_VMIC4140:0_Ch23 0 23 HRSE_DTECTR_VMIC4140:0_Ch24 0 24 HRSE_DTECTR_VMIC4140:0_Ch25 0 25 HRSE_DTECTR_VMIC4140:0_Ch26 0 26 HRSE_DTECTR_VMIC4140:0_Ch27 0 27 HRSE_DTECTR_VMIC4140:0_Ch28 0 28 HRSE_DTECTR_VMIC4140:0_Ch29 0 29 HRSE_DTECTR_VMIC4140:0_Ch30 0 30 HRSE_DTECTR_VMIC4140:0_Ch31 0 31 --------------------------------------------------------------------- # # Signal | Card | Sgn | #--------------------------|------|-----| HacRICH_VMIC4140:0_Ch0 0 0 HacRICH_VMIC4140:0_Ch1 0 1 --------------------------------------------------------------------- # # Signal | Card | Sgn | #--------------------------|------|-----| Harm_C0Top_Tc 0 0 Harm_C1Top_Tc 0 1 Harm_C2Top_Tc 0 2 Harm_C3Top_Tc 0 3 Harm_C3Bot_Tc 0 4 Harm_C4Top_Tc 0 5 Harm_C4Bot_Tc 0 6 HrsH_VDC_cHVTop 0 7 HrsH_VDC_cHVBot 0 8 HacH_tVDC_DSClvl 0 9 HacH_bVDC_DSClvl 0 10