The figure below shows a block diagram of the controller. The CAMAC tasks are executed by the microprocessor (Motorola 68030) or by the VIC Interface (status checking, block transfer control: Q Stop, Q Scan, ...). The controller complies with the CAMAC EUR 6500 specifications, and can also be used as an auxiliary controller, in order to give a smooth migration from existing CAMAC systems to a state-of-the-art equipment.To uncouple the VICbus read-out from the internal operation of the microprocessor, a dual port RAM has been implemented.
The CPU is optional. All resources can be accessed from the VIC Interface. The VICbus can be directly mapped to the NAF Command bits and some auxiliary control bits. This leads to a very simple and economic implementation which has sufficient performance for systems dedicated to control.
The CPU is able to build up data-packages inside the DPRAM, with data provided by the CAMAC modules. After completion of one data-package, the CPU generates an interrupt to the VIC slave interface which is now able to read the data in block transfer mode.
The VICbus interface is slave only with interrupt generation capability and supports the auto-address increment mode to pass blocks of data to or from several contiguously addressed locations of the dual port RAM. Only the address of the first location is specified, and thereafter the actual address is incremented during a Read or Write cycle. The VICbus controller part has been implemented by standard logic devices, PLD's and a special gate array from CES.
