/*************************************************************************************************
 *** Copyright (C) Intel Corporation 2006
 *** All Rights Reserved.
 *** ---------------------------------------------------------------------------------------------
 *** PROJECT NAME: Intel StrataFlash(R) Cellular Memory (M18) Template Reference Code
 ***
 *** FILE:         target.c
 ***
 *** TARGET:  	   Motorola Coldfire* 5272 with custom M18 Add-on sockets
 ***
 *** VERSION:      1.0
 ***
 *** DATE:         03/24/06
 ***
 *** AUTHOR:       Ronald Richardson
 ***
 *** PURPOSE:      Implementation of target hardware-specific driver functionality. Includes
 ***			   definitions pertaining to the target system and this implementation.
 ***
 *** ---------------------------------------------------------------------------------------------
 *** General Note(s):
 ***
 *** 2.	This template driver has been written to support X16 devices only, and must be
 ***	heavily modified to support X32 devices.
 ***
 *** 3.	This file contains definitions specific to the Motorola Coldfire 5272 board
 ***	& Intel's customized expansion setup. The driver has not been tested on other
 ***	devices, and must be adopted to that hardware before use.
 ***
 *************************************************************************************************
 *** NOTICE OF LICENSE AGREEMENT
 ***
 *** This code is provided by Intel Corp., and the use is governed
 *** under the terms of a license agreement. See license agreement
 *** for complete terms of license.
 ***
 *** YOU MAY ONLY USE THE SOFTWARE WITH INTEL FLASH PRODUCTS. YOUR
 *** USE OF THE SOFTWARE WITH ANY OTHER FLASH PRODUCTS IS EXPRESSLY
 *** PROHIBITED UNLESS AND UNTIL YOU APPLY FOR, AND ARE GRANTED IN
 *** INTEL'S SOLE DISCRETION, A SEPARATE WRITTEN SOFTWARE LICENSE
 *** FROM INTEL LICENSING ANY SUCH USE.
 *************************************************************************************************/

#include "target.h"

/*******************************************************************************************
 ***     MCF5272 GPIO to Address Pins Mapping Setup => See Note 2.
 *******************************************************************************************/

/*-----------------------------------------------------------------------------------------*
 | Addressing Constants
 |
 | 	The MCF5272 only supports address pins [0,21] given the current configuration. The other
 |	six address pins, as well as several control signals, are driven by the GPIO unit on
 |	the target hardware. The following definitions are used when dealing with these
 |	superfluous bits:
 |
 *-----------------------------------------------------------------------------------------*/

/* Base address for Coldfire* control registers */
#define TMPL_CF_MBAR					(0x40000000)

/* The largest address that can be sent to the board without using GPIO */
#define TMPL_ADJUNCT_ADDR_STANDARD		0x003FFFFF

/* MCF5272's GPIO address for driving these address lines: Coldfire PADAT register */
#define TMPL_ADJUNCT_ADDR_LOC			( *((volatile uint16 *)(TMPL_CF_MBAR + 0x86)) )

/* Bit mask to discard any higher-order bits before writing to ADDR_LOC */
#define TMPL_ADJUNCT_ADDR(topBits)		(0x3F & (topBits))

/* Single address pin locations: GPIO DAT lines 0 through 5 */
#define TMPL_ADJUNCT_ADDR_BIT_22		(0x0001)
#define TMPL_ADJUNCT_ADDR_BIT_23		(0x0002)
#define TMPL_ADJUNCT_ADDR_BIT_24		(0x0004)
#define TMPL_ADJUNCT_ADDR_BIT_25		(0x0008)
#define TMPL_ADJUNCT_ADDR_BIT_26		(0x0010)
#define TMPL_ADJUNCT_ADDR_BIT_27		(0x0020)

/* M18 chip select given we have two available sockets: Coldfire PBDAT control register */
#define TMPL_M18_CTRL					( *((volatile uint16 *)(TMPL_CF_MBAR + 0x8E)) )

/* Other signals and their locations: From GPIO DAT register locations */
#define TMPL_M18_WP						(0x0800)
#define TMPL_M18_RB						(0x2000)
#define TMPL_M18_nCS_SEL				(0x4000)
#define TMPL_M18_CS_SEL					(0x0100)

/* Chip Select No. 2: From Coldfire CSBR and CSOR # 2 registers */
#define TMPL_CS_CSBR2					( *((volatile uint32 *)(TMPL_CF_MBAR + 0x50)) )
#define TMPL_CS_CSOR2					( *((volatile uint32 *)(TMPL_CF_MBAR + 0x54)) )
#define TMPL_CS_BR_BASE(addr)			((addr) & 0xFFFFF000)
#define TMPL_CS_BR_PS_16				(0x0200)
#define TMPL_CS_BR_SRAM					(0x0000)
#define TMPL_CS_BR_EN					(0x0001)

#define TMPL_CS_OR_MASK_8M				(0xFF800000)
#define TMPL_CS_OR_WS(data)				(((data)&0x1F)<<2)

/* GPIO Control Registers and bit masks: Controlling extra address pins of device */
#define TMPL_GPIO_PACNT					( *((volatile uint32 *)(TMPL_CF_MBAR + 0x80)) )
#define TMPL_GPIO_PBCNT					( *((volatile uint32 *)(TMPL_CF_MBAR + 0x88)) )

#define TMPL_GPIO_PADDR					( *((volatile uint16 *)(TMPL_CF_MBAR + 0x84)) )
#define TMPL_GPIO_PBDDR					( *((volatile uint16 *)(TMPL_CF_MBAR + 0x8C)) )

#define TMPL_GPIO_DDR14_OUTPUT			(0x4000)
#define TMPL_GPIO_DDR13_INPUT			(~0x2000)
#define TMPL_GPIO_DDR11_OUTPUT			(0x0800)
#define TMPL_GPIO_DDR8_OUTPUT			(0x0100)
#define TMPL_GPIO_DDR5_OUTPUT			(0x0020)
#define TMPL_GPIO_DDR4_OUTPUT			(0x0010)
#define TMPL_GPIO_DDR3_OUTPUT			(0x0008)
#define TMPL_GPIO_DDR2_OUTPUT			(0x0004)
#define TMPL_GPIO_DDR1_OUTPUT			(0x0002)
#define TMPL_GPIO_DDR0_OUTPUT			(0x0001)


/*******************************************************************************************
 ***     Platform Expansion Slot Addresses
 *******************************************************************************************/

/* Base address of device within Coldfire memory space: */
#define TMPL_NOR_DIE_1_ADDR				0x60000000


/*******************************************************************************************
 ***     Target Method Implementations
 *******************************************************************************************/

void TMPL_InitHardware() {

	/* Chip Select 2 - Set to NOR die #1 */
	TMPL_CS_CSBR2 = (0
		| TMPL_CS_BR_BASE(TMPL_NOR_DIE_1_ADDR)
		| TMPL_CS_BR_SRAM
		| TMPL_CS_BR_PS_16
		| TMPL_CS_BR_EN);
	TMPL_CS_CSOR2 = (0
		| TMPL_CS_OR_MASK_8M
		| TMPL_CS_OR_WS(6));


	/* Configure GPIO */
	TMPL_GPIO_PACNT &= 0xFFFFF000;
	TMPL_GPIO_PBCNT &= 0xC33CFFFF;

	/* Initialize data values */
	TMPL_ADJUNCT_ADDR_LOC &= TMPL_ADJUNCT_ADDR(0);
	TMPL_M18_CTRL = (TMPL_M18_CTRL & (~TMPL_M18_nCS_SEL)) | TMPL_M18_WP | TMPL_M18_CS_SEL;
	/* M18 WP is 1 */

	/* Set GPIO directions */
	TMPL_GPIO_PADDR	|= (TMPL_GPIO_DDR0_OUTPUT
						|	TMPL_GPIO_DDR1_OUTPUT
						|	TMPL_GPIO_DDR2_OUTPUT
						|	TMPL_GPIO_DDR3_OUTPUT
						|	TMPL_GPIO_DDR4_OUTPUT
						|	TMPL_GPIO_DDR5_OUTPUT);

	TMPL_GPIO_PBDDR =  (TMPL_GPIO_PBCNT & TMPL_GPIO_DDR13_INPUT)
						|  (TMPL_GPIO_DDR8_OUTPUT
						|	TMPL_GPIO_DDR11_OUTPUT
						|	TMPL_GPIO_DDR14_OUTPUT);
}



void TMPL_WriteWord(const flash_info * info, uint32 addr, uint16 word) {
	/* If any of the 'extra' address bits are referenced, we must drive them with GPIO */
	if (addr > TMPL_ADJUNCT_ADDR_STANDARD) {

		/* Setting extra address bits to all zeros, then flipping desired bits: */
        TMPL_ADJUNCT_ADDR_LOC &= TMPL_ADJUNCT_ADDR(0);
		TMPL_ADJUNCT_ADDR_LOC |= TMPL_ADJUNCT_ADDR(addr >> 22);

		/* GPIO is driving other address lines */
		info->baseAddr[addr & TMPL_ADJUNCT_ADDR_STANDARD] = word;

		/* Return extra address bits to zero */
		TMPL_ADJUNCT_ADDR_LOC &= TMPL_ADJUNCT_ADDR(0);
	} else {
		/* Standard write */
		info->baseAddr[addr] = word;
	}
}



/* NOTE: Should be made 'inline' if possible depending on target compiler: */
uint16 TMPL_ReadWord(const flash_info * info, uint32 addr) {
	uint16 retValue;
	/* If any of the 'extra' address bits are referenced, we must drive them with GPIO */
	if (addr > TMPL_ADJUNCT_ADDR_STANDARD) {

		/* Setting extra address bits to all zeros, then flipping desired bits: */
        TMPL_ADJUNCT_ADDR_LOC &= TMPL_ADJUNCT_ADDR(0);
		TMPL_ADJUNCT_ADDR_LOC |= TMPL_ADJUNCT_ADDR(addr >> 22);


		retValue = info->baseAddr[addr & TMPL_ADJUNCT_ADDR_STANDARD];

		/* Return extra address bits to zero */
		TMPL_ADJUNCT_ADDR_LOC &= TMPL_ADJUNCT_ADDR(0);
	} else {
		/* Standard read */
		retValue = info->baseAddr[addr];
	}
	return retValue;
}