LeCroy 1880 Series (1885N/1882N) 96 Channel Integrating ADC

FASTBUS Series 1880 96 Channel Gated Integrating ADC

The FASTBUS Series 1880 contains 96 channels of ADC with current integrating negative inputs. Model 1882N offers 12-bit operation while the 1885N offers the equivalent dynamic range of a 15-bit linear ADC.

Gated integrating ADC's provide high flexibility. The use of gated integrators allows the shaping time of the system to be determined at run time. The same ADC can be used to encode photomultiplier and chamber signals or to sample slowly varying signals. DC-coupled, gated integrators are best suited to high rate applications, especially when a wide dynamic range is required.

The 96 inputs are received via two 100-pin pc edge connectors. The input has been designed to accept signals via two pc paddle cards, simplifying the routing of cables. The input reference (signal ground) may be isolated from the module ground for low frequencies. This jumper selectable option provides common mode noise rejection and hence minimizes the effect of ground loops.

The 1880 Series may be used with the optional Model 1810 CAT module to provide the Calibration And Trigger signals required by the ADC. Operation without a CAT is also possible using the software-selectable front-panel Gate and Fast Clear Inputs. Strobe Fan-Outs and the calibration voltage however, must then be supplied by the user. The readout of the 1880 Series is in accordance with the FASTBUS Standard, so modules may be read out via Standard FASTBUS hardware such as a Segment Interconnect (SI), or a Model 1821 FASTBUS Segment Manager/Interface (SM/I).

The conversion time of the 1880 Series ADC is less than 750 usec. A faster option (300 usec) is available on request. Readout, including pedestal subtract, can be accomplished in 15 usec via a hardware hand- shake feature in the LeCroy FASTBUS Model 1821 Segment Manager/Interface.

INPUT CIRCUIT
The input circuit employs 24 of the 4-channel Charge Multiplexers (QMUX) MIQ400 Series monolithic circuits. The QMUX is designed to supply the integrate-and-store function as well as the output multiplexing to the common integrator and ADC.

Each input signal is split into three parts called "low range"(80% of the input signal), "high range"(10% of the input signal) and "current sum" (10% of the input signal). Note that the current sum is an ungated signal whereas the rest of the signals are gated, integrated and held inside the QMUX. For details, see the MIQ401 data sheet.

CONVERSION TECHNIQUE
In order to cover a wide dynamic range with a single 12-bit ADC, the Model 1885N ADC uses a dual range technique. See graph below. This scheme allows less than 1% quantization error from 5 pC to 1450 pC and corresponds to 15 bits of dynamic range.

For input signals less than ~=180 pC the 1885N ADC digitizes the signal with a resolution of 50 fC per count. For signals between ~=175 and 1450 pC the resolution is 400 fC/count. The digitized output from each channel consists of a 12-bit amplitude word and a range bit (13th bit). The user can select "low range", "high range"or "auto range" under program control.

ANALOG OUTPUT
Twenty-four sum output signals may be used for triggering. They are routed to the FASTBUS Auxiliary Connector. Each of these 24 signals is 10% of the ungated sum of a group of 4 adjacent channels. The output stages are open collectors, allowing further summing to be easily performed. The 1880 Series modules also provide power and control at the Auxiliary Connector.

CALIBRATION
The Series 1880 employs a calibration circuit allowing the gain of all ADC channels to be measured to better than 1.5%. The calibration circuits are Voltage-programmed pulse generators. A DC level (Test Ref) is bused from the 1810 CAT module to all 1880 Series modules within the FASTBUS crate using the FASTBUS UR lines. When calibra- tion is enabled via CSR 0, the leading edge of the gate causes a well defined amount of charge (proportional to the Test Ref Level) to be deposited in each of the ADC inputs.

Specifications

Type:

Gated Current-integrating

Channels:

96

Input:

Quasi-differential. Impedance 50 ohm +/- 5%. Protected to +/- 100 V for 1 usec.

Input connector:

Two 100-pin pc edge connectors AMP 583900-3 or equivalent. For input paddle cards, consult the factory for manufacturing documentation package information.

CMRR:

>50 dB for +/- 200 mV DC to 1 kHz

Pedestal:

Maximum: 950 counts At 1500 usec gate width. If narrower gates are used the pedestal

Nominal: 500 counts spread reduces and the board pedestal trimpot may be readjustable

Full-Scale Charge:

Minimum: 100 counts ted to give a lower nominal pedestal.

1882:

175 pC (1450 pC full scale range by special factory option Model 1882N/100).

1885 Low Range:

175 pC

1885 High Range:

1450 pC

Sensitivity:

Figures given are for nominal pedestal.

1882:

50 fC/count +/- 3%

1885 (Bi-linear):

Low range: 50 fC/count +/- 3%

High range: 400 fC/count +/- 3%

Integral Non-Linearity:

< +/- (0.25% of reading + 2 counts) on low range; <+/-(O.5% of reading + 2 counts) on high range.

Operating Region:

+ 10 mV to - 1.5 V for specified linearity, (+ 0.2 to - 30 mA into 50 Q).

Gate Input:

Differential ECL input via a 2-pin front-panel connector or via TR1 (B47) and TR2 (B48) lines on the FASTBUS backplane. May be driven by the Model 1810 CAT Module. TR1 is the positive input. Width: 50 nsec to 2 usec. Uses removable termination resistor for busing of more than one module.

Fast Clear:

Differential ECL input via a 2-pin front-panel connector or a single-ended ECL signal via TRO (B46) line on FASTBUS backplane which may be driven by the Model 1810 CAT module. May be executed at any time. Settles to within (0.1% of reading + 1 count) within 600 nsec. Minimum width: 50 nsec. Uses removable termination resistor for busing of more than one module.

Noise:

0.8 counts rms typ. <2 counts max.

Interchannel Isolation:

75 dB typ., >60 dB min.

Calibration Feature:

Allows the gain of any channel to be measured to within +/- 1.5%. Needs an external DC voltage and a gate signal. The charge pulse applied to all channels is proportional to the DC voltage across the differential Test Level Inputs (UR1 is the positive input) on the FASTBUS backplane. Voltage range: 0 to 10 V. The calibration coefficient is 160 pC/V.

Temperature Coefficient:

< +/- (0.1% of reading + 1 count)/OC

Long Term Stability:

+/- (0.25% of reading + 10 counts)/Week

Power Dissipation:

<0.40 W/channel

Fast Analog Output:

24 ungated current sum signals on Auxiliary FASTBUS conector. Signal shape: same as analog input; signal amplitude = 0.1 times input signal amplitude. Output impedance: =>100 k ohm. Output compliance: 4 to 7 V

ADC:

12 bits

Conversion Time:

<750 usec for all 96 channels (<300 usec available at extra cost) Measure Pause Interval Input: Single-ended ECL signal via TR5 (B51) line on FASTBUS backplane. May be driven by the Model 1810 CAT Modules. Defines when conversion starts, if enabled by program. Can be applied up to 300 usec after gate.

Packaging:

Single-width FASTBUS module in conformance with FASTBUS Specification dated December 1983.

Power Requirements:

300 mA at + 15 V
3.4 A at + 5 V
1 A at -2V
2.8 A at - 5.2 V
100 mA at - 15 V

CONTROL FUNCTIONS IMPLEMENTED (CSR Space)

Module Identification Code:

Read Only. (1040)h for 1882N, (1041)h for 1885N.

Trigger Personality Programming:

Addressing supplied for sixteen 8-bit user-supplied registers.

Auto Range Select:

Sets the readout conversion mode to Auto Range.

Hi-Lo Range Select:

Fixes the readout conversion mode to high or low range.

Gate Source:

Selects either front panel or backplane.

MPI Source:

Selects internal monostable or backplane.

Test Enable:

Enables test mode

Memory Test:

Enables FASTBUS write to internal data buffer.

FASTBUS CONTROL Implemented Addressing

Modes:

Geographical, Secondary, Broadcast

Implemented Boadcast Functions:

Code

Significance

Comments

O1h*

General Broadcast Select

The ADC modules are selected and respond to subsequent data cycles.

09h

Sparse Data Scan (SDS)

ADC modules containing data assert their "T pin" on the following read data cycle.

09h

Pattern Select

ADCs seeing their T pin asserted on the following write data cycle become selected to respond to subsequent data cycles.

0Dh

All Device Scan

All ADC modules assert their T pin on the following read data cycle.

9Dh

ADC SDS

Unique Sparse Data Scan for 1880 Series modules only. Follows standard SDS (see above).

CDh

Personality Card SDS

Sparse Data Scan: ADC asserts T pin if Personality Card requires service.

Slave Status Responses to Data Cycles:

SS

Significance

0

Valid action

1

Busy

2

End of data

6

Error. Invalid mode

7

Error. Invalid Secondary Address loaded into internal address register.

*An h subscript indicates hexadecimal (base 16).

Pin Out Description:

ISUMj:

1/10 of the sum of the ungated input currents of four adjacent channels (O + 1 +2+ 3),(4+5+6+ 7).... (92 + 93 + 94 + 95). 0<=j <=23.

CLEAR:

ECL Fast Clear pulse. Active from 20 nsec after the time of application of the Fast Clear pulse at the CAT until 20 nsec after the next Gate Pulse.

GATE, GATE:

Differential ECL Conversion Gate Pulse. Occurs 20 nsec after the Gate is applied to the CAT Duration equal to the input pulse.

R/W:

Defines which operation, read or write, is strobed by UCSRSTR.

UCSRSTR:

UserCSR strobe. Applied when the user accesses (reads or writes) the CSR user space C0000OOh-CO00015h.

Aj:

Four-bit CSR user space address. Eg. CSR address C00001 h cor- responds to A = 1.

Dj:

Eight-bit data word.

NA (invalid Addr):

TTL high level applied to pin A38 from the Auxiliary Card indicates that the CSR register accessed is not implemented. The 1880 Series modules respond with SS = 7

PCSTR:

Personality Card Strobe, TTL level, active high.

PCT:

Personality Card Trigger, TTL level, active low.

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Type:	Gated Current-integrating
Channels:	96
Input:	Quasi-differential. Impedance 50 ohm +/- 5%. Protected to +/- 100 V for 1 usec.
Input connector:	Two 100-pin pc edge connectors AMP 583900-3 or equivalent. For input paddle cards, consult the factory for manufacturing documentation package information.
CMRR:	>50 dB for +/- 200 mV DC to 1 kHz
Pedestal:	Maximum: 950 counts At 1500 usec gate width. If narrower gates are used the pedestal
	Nominal: 500 counts spread reduces and the board pedestal trimpot may be readjustable
Full-Scale Charge:	Minimum: 100 counts ted to give a lower nominal pedestal.
1882:	175 pC (1450 pC full scale range by special factory option Model 1882N/100).
1885 Low Range:	175 pC
1885 High Range:	1450 pC
Sensitivity:	Figures given are for nominal pedestal.
1882:	50 fC/count +/- 3%
1885 (Bi-linear):	Low range: 50 fC/count +/- 3%
	High range: 400 fC/count +/- 3%
Integral Non-Linearity:	< +/- (0.25% of reading + 2 counts) on low range; <+/-(O.5% of reading + 2 counts) on high range.
Operating Region:	+ 10 mV to - 1.5 V for specified linearity, (+ 0.2 to - 30 mA into 50 Q).
Gate Input:	Differential ECL input via a 2-pin front-panel connector or via TR1 (B47) and TR2 (B48) lines on the FASTBUS backplane. May be driven by the Model 1810 CAT Module. TR1 is the positive input. Width: 50 nsec to 2 usec. Uses removable termination resistor for busing of more than one module.
Fast Clear:	Differential ECL input via a 2-pin front-panel connector or a single-ended ECL signal via TRO (B46) line on FASTBUS backplane which may be driven by the Model 1810 CAT module. May be executed at any time. Settles to within (0.1% of reading + 1 count) within 600 nsec. Minimum width: 50 nsec. Uses removable termination resistor for busing of more than one module.
Noise:	0.8 counts rms typ. <2 counts max.
Interchannel Isolation:	75 dB typ., >60 dB min.
Calibration Feature:	Allows the gain of any channel to be measured to within +/- 1.5%. Needs an external DC voltage and a gate signal. The charge pulse applied to all channels is proportional to the DC voltage across the differential Test Level Inputs (UR1 is the positive input) on the FASTBUS backplane. Voltage range: 0 to 10 V. The calibration coefficient is 160 pC/V.
Temperature Coefficient:	< +/- (0.1% of reading + 1 count)/OC
Long Term Stability:	+/- (0.25% of reading + 10 counts)/Week
Power Dissipation:	<0.40 W/channel
Fast Analog Output:	24 ungated current sum signals on Auxiliary FASTBUS conector. Signal shape: same as analog input; signal amplitude = 0.1 times input signal amplitude. Output impedance: =>100 k ohm. Output compliance: 4 to 7 V
ADC:	12 bits
Conversion Time:	<750 usec for all 96 channels (<300 usec available at extra cost) Measure Pause Interval Input: Single-ended ECL signal via TR5 (B51) line on FASTBUS backplane. May be driven by the Model 1810 CAT Modules. Defines when conversion starts, if enabled by program. Can be applied up to 300 usec after gate.
Packaging:	Single-width FASTBUS module in conformance with FASTBUS Specification dated December 1983.
Power Requirements:	300 mA at + 15 V 3.4 A at + 5 V 1 A at -2V 2.8 A at - 5.2 V 100 mA at - 15 V

CONTROL FUNCTIONS IMPLEMENTED (CSR Space)
Module Identification Code:	Read Only. (1040)h for 1882N, (1041)h for 1885N.
Trigger Personality Programming:	Addressing supplied for sixteen 8-bit user-supplied registers.
Auto Range Select:	Sets the readout conversion mode to Auto Range.
Hi-Lo Range Select:	Fixes the readout conversion mode to high or low range.
Gate Source:	Selects either front panel or backplane.
MPI Source:	Selects internal monostable or backplane.
Test Enable:	Enables test mode
Memory Test:	Enables FASTBUS write to internal data buffer.

FASTBUS CONTROL Implemented Addressing
Modes:	Geographical, Secondary, Broadcast
Implemented Boadcast Functions:	Code	Significance	Comments
	O1h*	General Broadcast Select	The ADC modules are selected and respond to subsequent data cycles.
	09h	Sparse Data Scan (SDS)	ADC modules containing data assert their "T pin" on the following read data cycle.
	09h	Pattern Select	ADCs seeing their T pin asserted on the following write data cycle become selected to respond to subsequent data cycles.
	0Dh	All Device Scan	All ADC modules assert their T pin on the following read data cycle.
	9Dh	ADC SDS	Unique Sparse Data Scan for 1880 Series modules only. Follows standard SDS (see above).
	CDh	Personality Card SDS	Sparse Data Scan: ADC asserts T pin if Personality Card requires service.
Slave Status Responses to Data Cycles:	SS	Significance
	0	Valid action
	1	Busy
	2	End of data
	6	Error. Invalid mode
	7	Error. Invalid Secondary Address loaded into internal address register.
*An h subscript indicates hexadecimal (base 16).

Pin Out Description:
ISUMj:	1/10 of the sum of the ungated input currents of four adjacent channels (O + 1 +2+ 3),(4+5+6+ 7).... (92 + 93 + 94 + 95). 0<=j <=23.
CLEAR:	ECL Fast Clear pulse. Active from 20 nsec after the time of application of the Fast Clear pulse at the CAT until 20 nsec after the next Gate Pulse.
GATE, GATE:	Differential ECL Conversion Gate Pulse. Occurs 20 nsec after the Gate is applied to the CAT Duration equal to the input pulse.
R/W:	Defines which operation, read or write, is strobed by UCSRSTR.
UCSRSTR:	UserCSR strobe. Applied when the user accesses (reads or writes) the CSR user space C0000OOh-CO00015h.
Aj:	Four-bit CSR user space address. Eg. CSR address C00001 h cor- responds to A = 1.
Dj:	Eight-bit data word.
NA (invalid Addr):	TTL high level applied to pin A38 from the Auxiliary Card indicates that the CSR register accessed is not implemented. The 1880 Series modules respond with SS = 7
PCSTR:	Personality Card Strobe, TTL level, active high.
PCT:	Personality Card Trigger, TTL level, active low.