LeCroy 1892 Multiple Record Buffer Memory

FASTBUS Model 1892 Multiple Record Buffer Memory

This single-width FASTBUS 1 megabyte memory module is intended to be used as a fast first-in first-out (FIFO) memory for 16 or 32-bit data from event based experiments. It may be used as a straight line FIFO, Linear Mode (see Figure 1) or as a rotary FIFO, Circular Mode (see Figure 2). The Model 1892 can also be used as a fast random access FASTBUS memory.

The 1892 accepts data via its front-panel ECLport using the ECLbus standard protocol. It is compatible with a variety of 16 and 32-bit data sources, including the Model 1821 FASTBUS Segment Manager/interface, the PCOS III MWPC System and the 4300 FERA ADC System. Data may also be written from the FASTBUS Seg- ment. The module has facilities to accept or overwrite (Fast Clear), the record being received via the ECLport.

The Model 1892 can output data to FASTBUS in the same order in which it was received at a combined read/write rate of <=20 megabyte/sec. Each record is stored in a block of contiguous memory locations. A Header Word is automatically written at the start of the record upon completion of data transmission (End of Record Signal). The Header contains a Record Valid flag bit, an ID number assigned to the event, user-set bits and a pointer to the address of the start of the next record. Control circuitry within the Model 1892 allows records to be read out or skipped one by one under FASTBUS control.

MEMORY SIZE
The memory has a capacity of 512K 16-bit words or 256K 32-bit words plus parity. A 1024K x 32-bit option is available. Due to memory chip availability, this extended memory option is cur- rently limited to an input rate of 3 megawordsisec.

DATA INPUT
A f ront-panel ECLport is employed to accept high-speed 16 or 32-bit data words using the ECLine standard. A CSR #O bit can be set and cleared to enable and disable the ECLport input.

DATA STORAGE
The Write Pointer register contains the destination of the next data word received. After each write, the Write Pointer is in- cremented. The end of a data record is signalled either by an End of Record strobe from the data source or by a FASTBUS command. A Record Header is then written as the first word of the record.

The Record Header contains four Flag Bits, an 8-bit event ID number and the 20-bit address of the header of the next record. The next header address is used to identify the end of the record during a block read. The event ID is used to distinguish records. When several memories are recording data from the same event the ID allows synchronization checks. The two user Flag Bits can be set from the front panel or from FASTBUS for a variety of purposes. Another Flag Bit indicates that the writing of the record has been completed and that it may be read. One Flag Bit is available as a software set Flag.

FAST CLEAR
A Write Abort command from either the front-panel input or FASTBUS disables data input until receipt of an End of Record input. The Write Abort also resets the Write Pointer to the start of the current record, thus releasing that part of memory for overwriting.

INPUT OVERFLOW WARNING On reaching an address equal to "end of memory less offset",
a front-panel differential ECL Full Warning ouput signal is generated. The offset may be user programmed. This signal can be used to terminate the flow of input data in an orderly manner. A CSR #0 bit is set by the Full Warning and another upon reaching End of Memory. In Circular Mode, the end of memory is defined by the value in the End of Memory register. In Linear Mode, it is the physical end of the memory.

DATA OUTPUT
Any word in the memory can be read directly by a FASTBUS single read from data space. The normal output mode, however, is the FASTBUS Block Transfer. Recognition of the block boun- daries can be enabled by transferring the Header into an End of Block register via FASTBUS. The Block Transfer will continue until the header of the next record is read when SS = 2 will be generated. A record can be reread by writing its header ad- dress to the Read Pointer. When the End of Memory is reached, SS = 3 is generated. If a parity error is detected dur- ing data ouput, SS = 7 is sent and a CSR #0 bit is set.

BLOCK SKIP
The Skip command may be sent via FASTBUS to set the End of Block register automatically. A further skip command will reset NTA and End of Block to read the record beyond the present one. Repeated Skip commands can be used to bypass any number of records.

LINEAR MODE
In linear FIFO Mode, each memory location is used once as a write location and once as a read location. The Read Pointer is always nearer the beginning of the memory than the Write Pointer. The pointers are only reset after all the data has been read. This mode is most useful for data which comes in bursts and sufficient memory is required to store nearly all the input data from a burst.

CIRCULAR MODE
If the data input source is continuous, it is possible to use the module as a circular FIFO. The header valid/invalid bit prevents the Read Pointer overtaking the Write Pointer. The End of Memory register provides protection against the Write Pointer overtaking the Read Pointer. Note that in Circular Mode, the "End of Memory' is an user-set variable and does not indicate the physical end. EOM should be located at the end of the last completely read record.

SEGMENT CONTROL VIA 1821 SM/I
A bidirectional Control Port is provided to facilitate the setup of a Model 1821 Segment Manager/interface, which may be the ECL data source when used as a Master in a FASTBUS crate. The port is written to and read as a CSR register. It pro- vides 30 single-ended TTL level signals at a front-panel mounted 34-pin connector. Fourteen bits are used to send con- trol signals to the 1821, the other 16 can send and receive data. One of the control bits sets the direction of data f low. 32-bit data can be sent from the 1821 to the 1892 by adding an 1821/ECL Auxiliary Card to the 1821.

Specifications

Unless specified all inputs are differential ECL level(>=4OOmV input swing),110 ohm +/- 10% impedance.High impedance by a simple user option.

FRONT-PANEL I/0 Data Inputs:

32 inputs grouped as two 16-bit words

Minimum pulse length:

50 nsec

Maximum data rate:

5.1 megawords/sec, 32-bit input 10.2 megawords/sec, 16-bit input. (60% of these ratios for extended memory option, 4 megawords)

Data Strobe:

Latches input data at the Auxiliary Port.

Minimum pulse length:

20 nsec

Minimum data set-up time:

0 nsec

Minimum data hold time:

50 nsec

End of Record Strobe:

Indicates data input over. Writes the Header. Disables Data Inputs for 3 usec maximum. Retains all words received before the strobe.

Minimum pulse length:

20 nsec

Write Abort Strobe:

Aborts the record being written. Resets Write Pointer to the start of the record.

Minimum Width:

20 nsec

User Flag Inputs:

See Record Header Format, above.

Minimum Width:

20 nsec

Flag A:

Differential ECL. A true level sets the Header A bit to 1.

Flag B.

Differential ECL. A true level sets the Header B bit to 1.

Flag A and B:

Differential ECL. A leading edge sets the A and B Header bits to 0.

Full Warning:

Differential ECL output via a front-panel 2-pin connector. Active as long as the Write Pointer lies between the values End of Memory and (End of Memory-Offset).

Full:

Differential ECL output via a front-panel 2-pin connector. Active as soon as the Write Pointer equals the End of Memory. Reset by the user.

Ready:

Differential ECL output via afront-panel 2-pin connector. Indicates that the module is able to accept input data; i.e., it is in Run mode, it is not carrying out an internal operation (End of Record, Write Abort, etc.) and it is not Full.

Control (SM/1) Port:

TTL-level front-panel port comprising a 16-bit bidirectional data bus and fourteen control lines. Used to control an 1821 SM/I from the Segment containing the 1892. This port has no effect on the operation of the 1892.

FRONT-PANEL INDICATORS

S

Slave activity indicator. Monostable-stretched to 100 msec minimum.

LM

Linear Mode

CM

Circular Mode.

FW

Full Warning. Indicates that the Full Warning output is active.

FL

Full. Indicates that the memory cannot accept more data.

RY

Ready. Indicates that the module is enabled to store input data.

ST

Strobe. Indicates the arrival of a Data Strobe input. Monostable-stretched to 100 msec minimum.

GENERAL

Memory Size:

512K 16-bit words or 256K 32-bit words plus one parity bit. Optional, 1024K 32-bit words at extra price (Model 1892/100).

Data Blocking:

A Record Header is written to memory at the start of a data record on receipt of a front- panel or FASTBUS End of Record command.

Header Format:

Four Flag Bits (3 user specified). Eight Record Identity Bits. Twenty Link Address Bits pointing to the start of the next record.

AS-AK Handshake Time:

30-55 nsec

DS-DK Handshake Time Single Transfers:

Read: 350-540 nsec
Write: 190-380 nsec

Block Transfers:

75-360 nsec

Mean Block Transfer Rate:

5.1 megawords/sec

NOTE: These times assume that the Auxiliary Port is idle during FASTBUS operations.

Power Requirements:

10 A at +5V
1.5 A at - 5.2 V

Packaging:

Single-width FASTBUS module in conformance with FASTBUS specification dated December, 1983, and April, 1985, supplement.

FASTBUS CONTROL

Addressing Modes:

Geographical, Logical, Broadcast. Logical Addressing uses a 16-bit Module Address and no Internal Address. All memory access is via Secondary Addressing.

Broadcast Functions:

A 16-bit Broadcast Class register is provided. Modules which recognize their Class will execute subsequent Write Cycles. This permits selected groups of modules to perform simultaneous control operations. The T-Pin activation command is also implemented.

Slave Status Responses to Data Cycles:

SS

Significance

0

Valid action

1

Busy.

2

Indicates the end ot a record during a Block Read.

3

End of Memory was reached during a Block Read or Write.

6

Error- Non-implemented command or action with invalid address.

7

Error-Invalid address written or memory parity error.

BIT ALLOCATIONS

CSR#O

Bit

Function

Type

0

Memory Parity Error

Status

1

Logical Address Enable

Mode Select

2

Run/Stop

Command

6

Block Flag

Mode Select

7

Circular Mode

Mode Select

8

Full Warning

Status

9

Full

Status

10

End of Record

Command

11

Write Abort

Command

12

Skip

Command

13

Mask Flag

Status

16-31

Module ID (1048)h*: Std. unit
(1049)h: 1024K option

Command

30

Master Reset
(i.e., CSR #O, 7 and 10h-15h)

Command

31

Clear Data
(i.e., CSR #11h, 13h, 15h)

Command

CSR REGISTER FUNCTIONS

CSR

Function

(3)h

Logical Address

(7)h

Broadcast Class

(1 O)h

Control (SM/1) Port Read/Write

(1 1)h

Write Pointer. Used as the Write Address for Auxiliary Port input. Increments automatically after each input word.

(1 2)h

Record Number. 8-bit register for record identification. Incremented automatically each time a header is written.

(1 3)h

End of Memory. Pointer to the first unavailable memory location.

(1 4)h

Offset. User-selected offset above End of Memory used to generate Full Warning.

(1 5)h

End of Block. Pointer to the first address not to be read in a Block Transfer.

FASTBUS OPERATIONS

Data Space Write:

Data can be written from FASTBUS using either single transters or Block Transfers. The user must generate appropriate header words to read the stored data in record format.

Data Space Read:

Both Single and Block Transfers are supported. Appropriate SS codes are generated to indicate End of Block, parity error and End of Memory. See above.

CSR Space Write:

Single Transfer and Broadcast modes are supported.

CSR Space Read:

Single Transfer mode is supported.

Addressing:

This module can be addressed Geographically and Logically and also responds to Broad- cast addressing. Secondary addressing is used for all access to Data Space which com- prises the 256K data words. (1024K in optional version).

*An h subscript denotes a hexadecimal number, i.e., base 16.

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Unless specified all inputs are differential ECL level(>=4OOmV input swing),110 ohm +/- 10% impedance.High impedance by a simple user option.
FRONT-PANEL I/0 Data Inputs:	32 inputs grouped as two 16-bit words
Minimum pulse length:	50 nsec
Maximum data rate:	5.1 megawords/sec, 32-bit input 10.2 megawords/sec, 16-bit input. (60% of these ratios for extended memory option, 4 megawords)
Data Strobe:	Latches input data at the Auxiliary Port.
Minimum pulse length:	20 nsec
Minimum data set-up time:	0 nsec
Minimum data hold time:	50 nsec
End of Record Strobe:	Indicates data input over. Writes the Header. Disables Data Inputs for 3 usec maximum. Retains all words received before the strobe.
Minimum pulse length:	20 nsec
Write Abort Strobe:	Aborts the record being written. Resets Write Pointer to the start of the record.
Minimum Width:	20 nsec
User Flag Inputs:	See Record Header Format, above.
Minimum Width:	20 nsec
Flag A:	Differential ECL. A true level sets the Header A bit to 1.
Flag B.	Differential ECL. A true level sets the Header B bit to 1.
Flag A and B:	Differential ECL. A leading edge sets the A and B Header bits to 0.
Full Warning:	Differential ECL output via a front-panel 2-pin connector. Active as long as the Write Pointer lies between the values End of Memory and (End of Memory-Offset).
Full:	Differential ECL output via a front-panel 2-pin connector. Active as soon as the Write Pointer equals the End of Memory. Reset by the user.
Ready:	Differential ECL output via afront-panel 2-pin connector. Indicates that the module is able to accept input data; i.e., it is in Run mode, it is not carrying out an internal operation (End of Record, Write Abort, etc.) and it is not Full.
Control (SM/1) Port:	TTL-level front-panel port comprising a 16-bit bidirectional data bus and fourteen control lines. Used to control an 1821 SM/I from the Segment containing the 1892. This port has no effect on the operation of the 1892.
FRONT-PANEL INDICATORS
S	Slave activity indicator. Monostable-stretched to 100 msec minimum.
LM	Linear Mode
CM	Circular Mode.
FW	Full Warning. Indicates that the Full Warning output is active.
FL	Full. Indicates that the memory cannot accept more data.
RY	Ready. Indicates that the module is enabled to store input data.
ST	Strobe. Indicates the arrival of a Data Strobe input. Monostable-stretched to 100 msec minimum.
GENERAL
Memory Size:	512K 16-bit words or 256K 32-bit words plus one parity bit. Optional, 1024K 32-bit words at extra price (Model 1892/100).
Data Blocking:	A Record Header is written to memory at the start of a data record on receipt of a front- panel or FASTBUS End of Record command.
Header Format:	Four Flag Bits (3 user specified). Eight Record Identity Bits. Twenty Link Address Bits pointing to the start of the next record.
AS-AK Handshake Time:	30-55 nsec
DS-DK Handshake Time Single Transfers:	Read: 350-540 nsec Write: 190-380 nsec
Block Transfers:	75-360 nsec
Mean Block Transfer Rate:	5.1 megawords/sec
NOTE: These times assume that the Auxiliary Port is idle during FASTBUS operations.
Power Requirements:	10 A at +5V 1.5 A at - 5.2 V
Packaging:	Single-width FASTBUS module in conformance with FASTBUS specification dated December, 1983, and April, 1985, supplement.

FASTBUS CONTROL
Addressing Modes:	Geographical, Logical, Broadcast. Logical Addressing uses a 16-bit Module Address and no Internal Address. All memory access is via Secondary Addressing.
Broadcast Functions:	A 16-bit Broadcast Class register is provided. Modules which recognize their Class will execute subsequent Write Cycles. This permits selected groups of modules to perform simultaneous control operations. The T-Pin activation command is also implemented.
Slave Status Responses to Data Cycles:	SS	Significance
	0	Valid action
	1	Busy.
	2	Indicates the end ot a record during a Block Read.
	3	End of Memory was reached during a Block Read or Write.
	6	Error- Non-implemented command or action with invalid address.
	7	Error-Invalid address written or memory parity error.
BIT ALLOCATIONS
CSR#O	Bit	Function	Type
	0	Memory Parity Error	Status
	1	Logical Address Enable	Mode Select
	2	Run/Stop	Command
	6	Block Flag	Mode Select
	7	Circular Mode	Mode Select
	8	Full Warning	Status
	9	Full	Status
	10	End of Record	Command
	11	Write Abort	Command
	12	Skip	Command
	13	Mask Flag	Status
	16-31	Module ID (1048)h*: Std. unit (1049)h: 1024K option	Command
	30	Master Reset (i.e., CSR #O, 7 and 10h-15h)	Command
	31	Clear Data (i.e., CSR #11h, 13h, 15h)	Command

CSR REGISTER FUNCTIONS
CSR	Function
(3)h	Logical Address
(7)h	Broadcast Class
(1 O)h	Control (SM/1) Port Read/Write
(1 1)h	Write Pointer. Used as the Write Address for Auxiliary Port input. Increments automatically after each input word.
(1 2)h	Record Number. 8-bit register for record identification. Incremented automatically each time a header is written.
(1 3)h	End of Memory. Pointer to the first unavailable memory location.
(1 4)h	Offset. User-selected offset above End of Memory used to generate Full Warning.
(1 5)h	End of Block. Pointer to the first address not to be read in a Block Transfer.
FASTBUS OPERATIONS
Data Space Write:	Data can be written from FASTBUS using either single transters or Block Transfers. The user must generate appropriate header words to read the stored data in record format.
Data Space Read:	Both Single and Block Transfers are supported. Appropriate SS codes are generated to indicate End of Block, parity error and End of Memory. See above.
CSR Space Write:	Single Transfer and Broadcast modes are supported.
CSR Space Read:	Single Transfer mode is supported.
Addressing:	This module can be addressed Geographically and Logically and also responds to Broad- cast addressing. Secondary addressing is used for all access to Data Space which com- prises the 256K data words. (1024K in optional version).
*An h subscript denotes a hexadecimal number, i.e., base 16.