4518 PROGRAMMABLE LOGIC DELAY/FAN-OUT
- High-Speed First Level Trigger Decisions
- Programmable Logic Functions
- Compatible with ECLine Data Handler Modules
- Compatible with ECLine Discriminators, ADC/TDC & MWPC Systems
- Designed-in Expandability
FAST, FIRSTLEVEL TRIGGER PROCESSING
The LeCroy ECLine programmable logic module family includes logic delays,
Boolean logic and other functions vital for high speed trigger systems.
It also includes fast table lookup permitting pre-programmed responses to
digital data. Functions are performed in only a few tens of nanoseconds,
permitting data to be screened prior to recording and increasing the sensitivity
of the experiment.
FUNCTIONAL DESCRIPTION
LeCroy's ECLine programmable logic modules are designed to quickly characterize
data so that a decision can be made for further processing. For example,
discriminators are employed to ensure that analog signals are of sufficient
amplitude to be interesting, and to provide logic outputs of fixed duration.
This stage is then followed by a coincidence latch which records the pattern
of "interesting signals" that occur within the same time window.
The first level trigger modules ensure that specific combinations of signals
have occurred. (Information on discrimina tors and latches may be found
on other ECLine data sheets.)
This first stage of data handling can then either reject the event as uninteresting,
or can pass data on for further processing. The more sophisticated line
of ECLine Data Handling modules include data conversion, arithmetic operations,
fast "do loop" type operations, and specialized pattern recognition.
Information on LeCroy data handling modules may be found on the data handlers
technical data sheet. All functions are programmable to provide complete
computer control of the triggering and data acquisition systems.
The LeCroy ECLine modules are compatible with several systems using ECL
bus such as the FERA (Fast Encoding and Readout ADC) system, 1821 based
FASTBUS systems as well as with the PCOS 3 System. These systems can interface
to VME via the LeCroy VME Dual Port Memory Model 1190.
Model 4518 (formerly 4418) Programmable Logic Delay/Fan-Out
Fast, passive logic delays are important when signals must arrive simultaneously
at a data acquisition module. The LeCroy Model 4518 has 16 passive, tapped
delay lines, one for each input. Each delay is individually set by computer
via CAMAC in 1, 2 or 8 nsec increments (depending on sub-model or "MOD"
selected), over a range of fifteen increments. The selection directs an
output to "use" a particular tap on the delay line. This would
give a means of accurately aligning signals in time, for example, to compensate
for differences in cable lengths.
Dead timeless operation at speeds up to 100 MHz is assured by using passive
delay lines and ECL switches. This feature provides the reliability of cable
delays together with the speed and fan-out of ECL circuitry. Each output
is available three places on the front panel to provide fan-out. The cost
of this device rivals cable delays.
SPECIFICATIONS
Model 4518 (formerly 4418) Programmable Logic Delay/Fan-Out
Inputs: 16, DC coupled 110 ohm ±5% impedance, on 34-pin header
for ECL signals; 100 MHz maximum rate (> 35MHz for 4518/300), < 10
nsec double pulse resolution (< 30 nsec for 4518/300). Minimum width:
5 nsec, (15 nsec for 4518/300).
Delay: 1-16 nsec in 1 nsec steps (4518), 2-32nsec in 2 nsec steps
(4518/100), 8-128 nsec in 8nsec steps (4518/300). Delays set by computer
for each channel individually.
Outputs: Three for each input, on three 34-pin headers, for compatibility
with complementary ECL devices. Width equal to input duration ±1.2
nsec (±4 nsec 4518/300). Rise time and fall time: 2.5nsec.
Crosstalk: Synchronous pulses in adjacent channels can be affected
by ±1 nsec typical.
Power: 50 mA at +6 V; 2.5 A at -6 V (15.3 W total).
CAMAC COMMANDS
Model 4518 (formerly 4418) Programmable Logic Delay/Fan-Out
CAMAC COMMANDS
X, Q: An X and Q response are generated when a valid N, A, F command
is recognized.
CAMAC FUNCTION CODES
F(16)·A(0-15): Load delay time setting on write lines W1 to W4.
One subaddress for each channel.
Copyright© September 1995. LeCroy is a registered trademark of
LeCroy Corporation. All rights reserved. Information in this publicaction
supersedes all earlier versions.