4564 OR LOGIC UNIT

High-Speed First Level Trigger Decisions
Programmable Logic Functions
Compatible with ECLine Data Handler Modules
Compatible with ECLine Discriminators, ADC/TDC & MWPC Systems
Designed-in Expandability

FAST, FIRSTLEVEL TRIGGER PROCESSING

The LeCroy ECLine programmable logic module family includes logic delays, Boolean logic and other functions vital for high speed trigger systems. It also includes fast table lookup permitting pre-programmed responses to digital data. Functions are performed in only a few tens of nanoseconds, permitting data to be screened prior to recording and increasing the sensitivity of the experiment.

FUNCTIONAL DESCRIPTION

LeCroy's ECLine programmable logic modules are designed to quickly characterize data so that a decision can be made for further processing. For example, discriminators are employed to ensure that analog signals are of sufficient amplitude to be interesting, and to provide logic outputs of fixed duration. This stage is then followed by a coincidence latch which records the pattern of "interesting signals" that occur within the same time window. The first level trigger modules ensure that specific combinations of signals have occurred. (Information on discriminators and latches may be found on other ECLine data sheets.)

This first stage of data handling can then either reject the event as uninteresting, or can pass data on for further processing. The more sophisticated line of ECLine Data Handling modules include data conversion, arithmetic operations, fast "do loop" type operations, and specialized pattern recognition. Information on LeCroy data handling modules may be found on the data handlers technical data sheet. All functions are programmable to provide complete computer control of the triggering and data acquisition systems.

The LeCroy ECLine modules are compatible with several systems using ECL bus such as the FERA (Fast Encoding and Readout ADC) system, 1821 based FASTBUS systems as well as with the PCOS 3 System. These systems can interface to VME via the LeCroy VME Dual Port Memory Model 1190.

Model 4564 OR Logic Unit

The Model 4564 is a simple and versatile logic module. It consists of four groups (A, B, C and D) of 16 input ORs followed by a set of additional 2-fold and 4-fold OR and AND functions. These various logic outputs, shown pictorially below, are simultaneously available on a rear-panel connector. The transit time is independent of the function. In addition, the outputs are capable of rates in excess of 100MHz. Output width is dependent on the input pulse overlap.

For greater flexibility, the 4564 also offers four discriminator/shaper channels. Internal jumpers allow any of the 12 logic combinations to be input to these channels. The output of discriminators/shapers can be triggered on the leading or tailing edge of the input (jumper selectable). The width is adjustable from 15nsec to greater than 500nsec. Output polarity is also selectable via internal switches. These outputs can be used simply as an adjust able width logic fan-out or can allow for more sophisticated functions.

A typical application of the 4564 is to perform a simple track or pattern recognition for Veto or gate applications.

Model 4564 Logic Diagram

SPECIFICATIONS

Model 4564 OR Logic Unit

Inputs: 64 in four 34-pin front-panel connectors, ECL signals, 110ohm impedance. Minimum width 6 nsec, maximum frequency > 100MHz.

Overlap Outputs: Rear-panel 34- pin connector, pins 1 to 12, ECL signals. Width corresponds to overlap (±2 nsec) of inputs of logic function, minimum output 5 nsec, maximum output frequency > 100 MHz; transit time 12 nsec ±1 nsec typical, independent of logic function; double pulse resolution 10nsec typical.

Shaped Outputs: Rear-panel connector pins 13 to 16, any of overlap logic can be converted via jumper option to any of the four discriminator/shapers, output is differential ECL levels and width is internally adjustable from 15 to > 500nsec, can be triggered in leading or trailing edge of inputs (jumper selectable); output polarity internally switch selectable; maximum frequency: 30MHz, double pulse resolution: 33nsec.

Power: 150 mA at +6 V; 1.5 A at -6 V; 20 mA at -24 V (10.4W total).

CAMAC COMMANDS

Model 4564 OR Logic Unit

The Model 4564 does not utilize CAMAC Commands or Function Codes.