Difference between revisions of "Preparation"
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| − | * Cable/HRS motion: add cable length and re-route the needed cables. Disconnect the others ? | + | * <span style="color:#ff0000"> Cable/HRS motion:</span> add cable length and re-route the needed cables. Disconnect the others ? |
| − | * Left cerenkov overflow: move ADC from ROC 3 to ROC 4. Could we split the signal between the existing ADC in ROC 3 and the ADC in ROC 4 ? | + | * <span style="color:#0000ff"> Left cerenkov overflow:</span> move ADC from ROC 3 to ROC 4. Could we split the signal between the existing ADC in ROC 3 and the ADC in ROC 4 ? <span style="color:#33cc00"> FIXED! </span> |
| + | Note(Zhihong): we are actually going to add a ADC card into ROC4 since there is a spare one in ROC3 Slot21, which is not included in the CRL code. We can simply take it out | ||
| + | and put it in ROC4, then move the Cereenkov cable to this card. So ROC3 will remain the same condition. | ||
| + | |||
| + | * <span style="color:#0000ff"> Left PRL2#14 overflow:</span> Will reduce it voltage at HV.Slot5.Ch7 (start with '0'), from -908V to -850V <span style="color:#33cc00"> FIXED! </span> | ||
| − | * Deadtime: | + | * <span style="color:#ff0000"> Deadtime:</span> |
- remove the sequencer reading of BB and only read the main trigger module. | - remove the sequencer reading of BB and only read the main trigger module. | ||
- or set hight threshold on unused channels. | - or set hight threshold on unused channels. | ||
| − | * Right arm Shower block 76 missing signal: check that it is at the bottom of the acceptance if cannot be fixed. | + | * <span style="color:#0000ff"> Right arm Shower block 76 missing signal:</span> check that it is at the bottom of the acceptance if cannot be fixed. <span style="color:#33cc00"> FIXED! </span> |
| − | * Right arm S1: one channel is noisy. | + | * <span style="color:#33cc00"> Right arm S1:</span> one channel is noisy. |
| + | Note(Zhihong): S1#2L has a noisy pedestal peak and I believe it could be because of a grounding issue with its connectors at patch panel. If there is another empty channel, we can | ||
| + | move this ADC cable to that, or just leave it as it if we can not fix it easily. | ||
| − | * Right arm Cerenkov: | + | * <span style="color:#0000ff"> Right arm Cerenkov:</span> [[ADC_PLOT]] <span style="color:#33cc00"> FIXED! </span> |
- multi-peak in the TDCs: gate width problem ? | - multi-peak in the TDCs: gate width problem ? | ||
| − | - no obvious single photon electron peak in ADCs: increase HV. | + | - no obvious single photon electron peak in ADCs: increase HV. [[New HVs]] |
| + | http://www.jlab.org/~adaq/halog/html/1103_archive/110310133121.html | ||
| + | |||
| + | Note(Zhihong): The gate width of all ADCs is set to be 270ns and the ADC signals of Cerenkove counters are amplified by 10 times through an Amplifier. | ||
| + | Through a scope, I can not see reflection of TDC signals but many noise peaks are above threshold(-30mV). The reason of multi-peaks might be because | ||
| + | those noise signals are triggered with real signals and | ||
| + | the 1775 multihits TDC treats the noise peaks as different hits but from the same events, hence we can not remove it by applying cunt on triggers and | ||
| + | ADCs. I will do more study | ||
| + | on it but since we do not need TDC of Cerenkov for offline analysis, we may can leave it with that if we can not solve it. | ||
| − | * Right Q3: run Q3 at momentum ?% lower for each momentum setting. | + | * <span style="color:#ff0000"> Right Q3:</span> run Q3 at momentum ?% lower for each momentum setting. |
| + | |||
| + | * <span style="color:#ff0000"> ROC3 still uses ADC gates from back panne </span> | ||
| + | http://www.jlab.org/~adaq/halog/html/1103_archive/110331111954.html | ||
Latest revision as of 16:10, 14 April 2011
- Cable/HRS motion: add cable length and re-route the needed cables. Disconnect the others ?
- Left cerenkov overflow: move ADC from ROC 3 to ROC 4. Could we split the signal between the existing ADC in ROC 3 and the ADC in ROC 4 ? FIXED!
Note(Zhihong): we are actually going to add a ADC card into ROC4 since there is a spare one in ROC3 Slot21, which is not included in the CRL code. We can simply take it out and put it in ROC4, then move the Cereenkov cable to this card. So ROC3 will remain the same condition.
- Left PRL2#14 overflow: Will reduce it voltage at HV.Slot5.Ch7 (start with '0'), from -908V to -850V FIXED!
- Deadtime:
- remove the sequencer reading of BB and only read the main trigger module.
- or set hight threshold on unused channels.
- Right arm Shower block 76 missing signal: check that it is at the bottom of the acceptance if cannot be fixed. FIXED!
- Right arm S1: one channel is noisy.
Note(Zhihong): S1#2L has a noisy pedestal peak and I believe it could be because of a grounding issue with its connectors at patch panel. If there is another empty channel, we can move this ADC cable to that, or just leave it as it if we can not fix it easily.
- Right arm Cerenkov: ADC_PLOT FIXED!
- multi-peak in the TDCs: gate width problem ?
- no obvious single photon electron peak in ADCs: increase HV. New HVs
http://www.jlab.org/~adaq/halog/html/1103_archive/110310133121.html
Note(Zhihong): The gate width of all ADCs is set to be 270ns and the ADC signals of Cerenkove counters are amplified by 10 times through an Amplifier.
Through a scope, I can not see reflection of TDC signals but many noise peaks are above threshold(-30mV). The reason of multi-peaks might be because
those noise signals are triggered with real signals and
the 1775 multihits TDC treats the noise peaks as different hits but from the same events, hence we can not remove it by applying cunt on triggers and
ADCs. I will do more study
on it but since we do not need TDC of Cerenkov for offline analysis, we may can leave it with that if we can not solve it.
- Right Q3: run Q3 at momentum ?% lower for each momentum setting.
- ROC3 still uses ADC gates from back panne
http://www.jlab.org/~adaq/halog/html/1103_archive/110331111954.html
