Difference between revisions of "DVCS3 crate and channel maps"

From Hall A Wiki
Jump to: navigation, search
(Copied the table of Intel CPU information from the page "DVCS3 DAQ")
Line 21: Line 21:
  
 
=== Modules in each crate ===  
 
=== Modules in each crate ===  
−
*  ROC27:  SIS3801 scalers "A" and "B"; CAEN V1190 TDC; ARS modules 0x1,0x2,0x3
+
*  ROC27:  SIS3801 scalers "A" and "B"; CAEN V1290 TDC; ARS modules 0x1,0x2,0x3
 
*  ROC28:  SIS3801 scaler "C"; ARS modules 0x4, 0x5, 0x6, 0x7, 0x8
 
*  ROC28:  SIS3801 scaler "C"; ARS modules 0x4, 0x5, 0x6, 0x7, 0x8
 
*  ROC29:  SIS3801 scaler "D"; ARS modules 0x9, 0xA, 0xB, 0xC, 0xD
 
*  ROC29:  SIS3801 scaler "D"; ARS modules 0x9, 0xA, 0xB, 0xC, 0xD
Line 28: Line 28:
 
*  ROC30:  SIS3801 scaler "E"; DVCS trigger readout card
 
*  ROC30:  SIS3801 scaler "E"; DVCS trigger readout card
  
−
== Channel layout for SIS3801 scalers "A" and "B" and CAEN V1190 TDC ==
+
== Channel layout for SIS3801 scalers "A" and "B" and CAEN V1290 TDC ==
−
The input signals for SIS3801 scalers "A" and "B" and CAEN V1190 TDC are daisy chained from "A", to "B", then terminate at the TDC.  Scalers "A" and "B" have had their internal termination resistors removed.  Both scalers are gated by the spectrometer scaler gate, but scaler "B" is further disabled by the DVCS trigger busy (which includes the TS busy).  Both scalers and the TDC are latched by a narrow pulse formed from the ARS_valid signal.
+
The input signals for SIS3801 scalers "A" and "B" and CAEN V1290 TDC are daisy chained from "A", to "B", then terminate at the TDC.  Scalers "A" and "B" have had their internal termination resistors removed.  Both scalers are gated by the spectrometer scaler gate, but scaler "B" is further disabled by the DVCS trigger busy (which includes the TS busy).  Both scalers and the TDC are latched by a narrow pulse formed from the ARS_valid signal.
  
 
# 512ns clock from DVCS trigger crate (1)
 
# 512ns clock from DVCS trigger crate (1)

Revision as of 15:53, 14 November 2014

Back to DVCS3

Crate layout in the DVCS racks

ROC info

Please see https://logbooks.jlab.org/entry/3292168 for information.

Model Mac1 location Hostname IP Adress ROC Hardware ID CODA ROC
VME 002038046D12 LHRS DVCS crate 1 intelhadvcs1 (ROC27) 129.57.192.80 4 27
VME 002038046DC1 LHRS DVCS crate 2 intelhadvcs2 (ROC28) 129.57.192.86 6 28
VME 0020CEF603EA LHRS DVCS crate 3 intelhadvcs3 (ROC29) 129.57.192.91 5 29
VME 002038046D0C LHRS DVCS crate 4 intelhadvcs4 (ROC30) 129.57.192.92 0 30
VME Upper level crate intelha3 7

Modules in each crate

  • ROC27: SIS3801 scalers "A" and "B"; CAEN V1290 TDC; ARS modules 0x1,0x2,0x3
  • ROC28: SIS3801 scaler "C"; ARS modules 0x4, 0x5, 0x6, 0x7, 0x8
  • ROC29: SIS3801 scaler "D"; ARS modules 0x9, 0xA, 0xB, 0xC, 0xD
  • DVCS trigger crate
  • NIM crate
  • ROC30: SIS3801 scaler "E"; DVCS trigger readout card

Channel layout for SIS3801 scalers "A" and "B" and CAEN V1290 TDC

The input signals for SIS3801 scalers "A" and "B" and CAEN V1290 TDC are daisy chained from "A", to "B", then terminate at the TDC. Scalers "A" and "B" have had their internal termination resistors removed. Both scalers are gated by the spectrometer scaler gate, but scaler "B" is further disabled by the DVCS trigger busy (which includes the TS busy). Both scalers and the TDC are latched by a narrow pulse formed from the ARS_valid signal.

  1. 512ns clock from DVCS trigger crate (1)
  2. DVCS cosmic trigger
  3. s0
  4. s2
  5. CER
  6. EDTM
  7. DVCS external clock or LED trigger
  8. ARS_stop
  9. ARS_valid
  10. DVCS calorimeter ADC_gate
  11. inverted S0
  12. inverted S2
  13. inverted CER
  14. L1A
  15. CaloBlock001
  16. External S2M_CER
  17. 64ns clock from DVCS trigger crate
  18. 512ns clock from DVCS trigger crate (2)
  25. Master_OR
  26. Master_OR_Live
  27. HRS_Single
  28. S2M_CER
  29. S2M_CER_Scaled
  31. 103kHz clock from spectrometer
  32. BCM signal
Retrieved from "https://hallaweb.jlab.org/wiki/index.php?title=DVCS3_crate_and_channel_maps&oldid=22845"