Difference between revisions of "Left HRS VDC T0 Drifts"
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[http://www.jlab.org/~adaq/halog/html/0811_archive/081118104840.html Study of VDC T0 Drift in HALOG] | [http://www.jlab.org/~adaq/halog/html/0811_archive/081118104840.html Study of VDC T0 Drift in HALOG] | ||
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[[Image:drift_pedI.gif]] | [[Image:drift_pedI.gif]] |
Revision as of 20:21, 21 November 2008
For the fifth pass production data, we can split the runs into three periods:
Period I: November 8 to November 11, runs: (3036-3203) Period II: November 12 to November 13, runs: (3304-3323) Period III: November 16 to present, runs: (3528-present)
During Period I, the T3 delay at the BigBite Weldment was set to 60 ns.
There is a short period of time, when the delay was 76 ns (runs 3117-3124).
None of these runs are production.
For Period II, all the T3 delay was removed and the T1 delay was changed
to move the coincidence peak into the middle of the window.
Period III began after the 2.5 day down due to the CHL problem. As far as we
know, there were no timing changes between Period II and III, however, re-timing
was set up for the BigBite triggers.
See Halog entry for further details on this figure:
Study of VDC T0 Drift in HALOG
'The next image'