Latest revision as of 11:44, 9 April 2007

Useful

Left arm detector stack phone 5151

Dead time calculation

General Information

Bob's to do list

Alex's to do list

For E04-018, TS was moved by Bob fron Left Arm to Right Arm to be able to have sufficient delays. This section will have informations about the changes made for this experiment. Since TS was moved were changed :

• cabling
• scalers
• delays
• Start of run / End of run

=Coincidence timing cabling= Bob's logbook page 34 RG213 on right ARM

• 1 T3
• 2 ? going into NIM ECL channel 4 (Lower left right crate ) to TS R Arm input 4 -> it's T4 !
• 3 labeled retiming from left arm to NIM lower left to PS715 discriminator channel 5 ( bottom module )to 7126 NIM/ECL channel 14 to R delay 2 channel 11 to NIM/ECL 7126 channel 15 (NIM left top slot 16 )to NIM/ECL (NIM right slot 3 channel 6) to FB 13 to TDC 1875 chan 32 , left arm retiming
• 4 Right arm retiming
• 5  ? going into NIM ECL channel output 14 (Lower left right crate ) wire pink and blue from TS L1A0
• 6 EDTM trigger

RG58

• 1 T1 Right
• 2 T5 from right to NIM/ECL on left ARM slot 9 left NIM crate PS 726 channel 14 to Fastbus 1877 slot 13 chan 51 ( black negative )
• 3 EDTM ?

File:Example.jpg

1875 Right Arm

Slot ROC 16

• 1
• 32 FB13 Left CT
• 34 FB3
• 37 FB5
• 43 FB12
• 47 FB4

=1877 Right Arm= slot 3 bottom crate slaot 15 FB6 T3 chan 0 FB19 T5 chan 1 Slot 12 FB18 T1 FB23 delay R1 chan 3

Ldelay

T4 Ledelay 1 output 7 input 7

=Rdelay1= From Bob's logbook May 2006 page 32

• 1-5 T1 Delay
• 6 unused
• 7-9 T2
• 10-12 unused
• 13 Cerenkov
• 14 S1
• 15 S2
• 16 Strobe S1orS2

Rdelay2

• 1-2 T3 to TS

3-5 unused 6-9 L1A

• 9 Right delayed L1A for RT
• 10-16 delay retiming left arm

Efficiency trigger, MLU

MLU inputs

• 0 RDelay 1 14
• 1 RDelay 1 15
• 2
• 3
• 4
• 5
• 6
• 7
• 8
• 9
• 10
• 11
• 12
• 13
• 14
• 15

MLU outputs

• 0
• 1 T2

Retiming signal Or of S1 and S2

OR S1 in NIM ECL (top crate )chan 1 OR S2 in NIM ECL (top crate )chan 3

both goes to logic module group 1 PS 757 bottom NIM where they are ORed on output goes to left arm for TC

other output delayed for RT

3rd output to NIM/ECL middle crate channel 16 ( green cable )

T1

• S1-OR -> 7126 NIM/ECL chan 1-green+ pink -> ECL Fan 1-yellow black -> Logic 4516 A1\
• S2-OR -> 7126 NIM/ECL chan 3 -green+ pink-> ECL Fan 3-yellow black -> Logic 4516 B1 /
• --> Logic 4516 output D1 red black cable- Black red -> ECL Fan 5

TS -> NIM/ECL chan 2 (right crate right slot )-> Nim ECL chan 12 ( middle crate )-> RDelay 1 chan 9 ->RDelay1 chan 8 -> RDelay 1 chan 7 -> R MLU output 1

T2

TS -> NIM/ECL chan 2 (right crate right slot )-> Nim ECL chan 12 ( middle crate )-> RDelay 1 chan 9 ->RDelay1 chan 8 -> RDelay 1 chan 7 -> R MLU output 1

T6

T6 = T3 and ( S1R or S2R )

Take retiming signal RT (Sl or S2 right arm ) loop through RDelay 1 chann 10 to 13 and arrive to logic module, where RT is AND with T3 ( T3 from discriminator to NIM ECL chan 3 to RDelay 2 chan 1 to NIM/ECL chan 13 to logic module for AND )

T7

T7 = T4 AND T1

Take delayed T1 fron RDelay1 chan 4 to NIM/ECL chan 1 to AND group 2) T4 from coax 2 to logic 8 to discriminator 2 to logic AND group 2)

Right arm FB cables

FB23 RDelay 1 output 3

Left arm coincidence time

Coax 4 retiming right arm Logic Fan (3ns cable) NIM ECL chan 14 TDC 1875 top crate ROC4 slot 25 chan 49

Table of modules and cables

[[1]]

Reset righht arm

ECL out 5 to ECL IN 6 NIM OUT 6 TTL to NIM IN 7 NIM out 7 to NIM/ECL IN 9 NIM ECL chan 8 out to ROC1 and ROC2

change

RDelay1 7 ECL 5 moved to ECL 11 Out 11 to NIM ECL 7 top